From 5ab9865fa6ed343ae0cffefb81b20af2e533e36f Mon Sep 17 00:00:00 2001 From: Jan Tuomi Date: Sat, 8 Apr 2023 17:20:32 +0300 Subject: Move from logisim to digital --- .vscode/launch.json | 2 +- digital/atk16.dig | 1470 +++++++++++++++++---------------------------- digital/atk16_alu.dig | 1290 +++++++++++++++++++-------------------- digital/atk16_decoder.dig | 402 +++++++++++++ digital/atk16_mem.dig | 461 ++++++++++++++ digital/atk16_regbank.dig | 1300 +++++++++++++++++++++++++++++++++++++++ high-level-lang-idea.perl | 36 ++ src/assembler.py | 57 +- src/test.atk16 | 2 +- src/test_sum.atk16 | 3 + src/ucode.py | 38 +- 11 files changed, 3424 insertions(+), 1637 deletions(-) create mode 100644 digital/atk16_decoder.dig create mode 100644 digital/atk16_mem.dig create mode 100644 digital/atk16_regbank.dig create mode 100644 high-level-lang-idea.perl create mode 100644 src/test_sum.atk16 diff --git a/.vscode/launch.json b/.vscode/launch.json index e60d76b..22dd52d 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -11,7 +11,7 @@ "program": "${file}", "console": "integratedTerminal", "justMyCode": true, - "args": ["test.atk16", "test.bin"] + "args": ["src/test.atk16", "out/test.bin"] } ] } \ No newline at end of file diff --git a/digital/atk16.dig b/digital/atk16.dig index 8c350c2..15912d7 100644 --- a/digital/atk16.dig +++ b/digital/atk16.dig @@ -1,29 +1,55 @@ 2 - + + + view1 + + + 0.8446671195652201 + 0.0 + 0.0 + 0.8446671195652201 + 481.55870489058793 + 445.5141438507956 + + + + + view2 + + + 0.8446671195652201 + 0.0 + 0.0 + 0.8446671195652201 + 481.55870489058793 + 445.5141438507956 + + + + + view3 + + + 0.8446671195652201 + 0.0 + 0.0 + 0.8446671195652201 + 481.55870489058793 + 445.5141438507956 + + + + - RegisterFile + Register - AddrBits - 3 + valueIsProbe + true - - Label - Register file - - - Bits - 16 - - - - - - Register - Label MAR @@ -39,33 +65,9 @@ Register - Label - IR - - - Bits - 16 - - - - - - atk16_alu.dig - - - Label - ALU - - - shapeType - SIMPLE + valueIsProbe + true - - - - - Register - Label FR @@ -138,261 +140,37 @@ NetName - IR_IE - - - - - - Tunnel - - - rotation - - - - NetName - IR_IE + PC_IE - Splitter - - - Input Splitting - 16 - - - Output Splitting - 3,3,3,3,4 - - - rotation - - - - - - - Tunnel - - - rotation - - - - NetName - OPCODE - - - - - - Tunnel - - - rotation - - - - NetName - IR0 - - - - - - Tunnel - - - rotation - - - - NetName - IR1 - - - - - - Tunnel - - - rotation - - - - NetName - IR2 - - - - - - Tunnel - - - rotation - - - - NetName - IR3 - - - - - - Tunnel - - - rotation - - - - NetName - IR0 - - - - - - Tunnel - - - rotation - - - - NetName - IR1 - - - - - - Tunnel - - - rotation - - - - NetName - IR2 - - - - - - Tunnel - - - rotation - - - - NetName - RW_IE - - - - - - Splitter - - - Input Splitting - 3,1 - - - Output Splitting - 4 - - - - - - Tunnel - - - rotation - - - - NetName - IR3 - - - - - - Tunnel - - - rotation - - - - NetName - OP_PARITY - - - - - - RAMAsync + EEPROM - - Label - MEM_RAM - AddrBits - 15 - - - Bits - 16 - - - - - - Tunnel - - - rotation - + 8 - - NetName - MEM_IE - - - - - - EEPROM - Label UCODE - - AddrBits - 8 - Bits 16 - isProgramMemory - true + Data + c,221,3040,8000,4*0,c,221,3040,8000,4*0,c,221,3040,8000,4*0,c +,221,3040,8000,4*0,c,221,88,60,8000,0,0,0,c,221,88,60,8000,0,0,0 +,c,221,88,110,8000,0,0,0,c,221,88,110,8000,0,0,0,c,221,440,8000 +,4*0,c,221,440,8000,4*0,c,221,82,8000,4*0,c,221,82,8000,4*0,c +,221,8000,5*0,c,221,102,8000,4*0,c,221,8000,5*0,c,221,8000,5*0 +,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c +,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221 +,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000 +,5*0,c,221,8000,5*0,c,221,4000,5*0,c,221,4000 @@ -402,86 +180,10 @@ Input Splitting - 3,1,4 - - - - - - VDD - - - rotation - - - - - - - Tunnel - - - rotation - - - - NetName - OPCODE - - - - - - Ground - - - rotation - - - - - - - BitSelector - - - Selector Bits - 2 - - - - - - Tunnel - - - rotation - - - - NetName - IR0 - - - - - - Splitter - - - rotation - - - - Input Splitting - 3 - - - Output Splitting - 2, + 3,1,4 - + VDD @@ -491,21 +193,7 @@ - - - - Counter - - - Label - Microsequencer - - - Bits - 3 - - - + Tunnel @@ -516,44 +204,30 @@ NetName - US_RS + OPCODE - - - - And - - + - VDD + Ground rotation - - - - Not - - + - Tunnel + BitSelector - rotation - - - - NetName - IR_L9 + Selector Bits + 2 - + Tunnel @@ -564,40 +238,50 @@ NetName - IR_L12 + FLAG_EQ - + Splitter + + rotation + + Input Splitting - 16 + 3 Output Splitting - 12, + 2, + + + + + VDD + rotation - + - + Splitter - - Input Splitting - 16 - mirror true + + Input Splitting + 16 + Output Splitting 1*16 @@ -608,6 +292,10 @@ CounterPreset + + valueIsProbe + true + Label PC @@ -638,7 +326,7 @@ rotation - + @@ -665,7 +353,7 @@ PC_CO - + Tunnel @@ -675,7 +363,7 @@ PC_IE - + Tunnel @@ -685,7 +373,7 @@ PC_OE - + Tunnel @@ -695,7 +383,7 @@ MAR_IE - + Tunnel @@ -705,7 +393,7 @@ MEM_IE - + Tunnel @@ -715,327 +403,332 @@ MEM_OE - + Tunnel NetName - RW_IE + R1_OE - + - Driver + Tunnel - flipSelPos - true - - - Bits - 16 + NetName + R2_OE - + - Driver + Tunnel - Bits - 16 - - - flipSelPos - true + NetName + IR_IE - + Tunnel NetName - R2_OE + JA_OE - + - Driver + Tunnel - Bits - 16 + NetName + ALU_OE - + Tunnel - - rotation - - NetName - ALU_OE + US_RS - + Tunnel NetName - R1_OE + FR_IE - + - Tunnel + Clock - NetName - R2_OE + small + true + + + runRealTime + true + + + Frequency + 10 - + Tunnel NetName - IR_IE + CLK - + Tunnel + + rotation + + NetName - R1_OE + CLK - + Tunnel + + rotation + + NetName - IR9_OE + CLK - + Tunnel + + rotation + + NetName - IR12_OE + CLK - + - Tunnel + Probe - NetName - ALU_OE + Label + Bus - + + + + atk16_mem.dig + + Tunnel + + rotation + + NetName - HALT + MEM_IE - + Tunnel + + rotation + + NetName - US_RS + MEM_OE - + - Tunnel + Break + + + + + atk16_decoder.dig - NetName - FR_IE + shapeType + SIMPLE - + - BitSelector + Tunnel - Selector Bits - 4 - - - rotation - - - - flipSelPos - true + NetName + OPCODE - + Tunnel rotation - + NetName - OP_PARITY + JA_OE - + - Const + Tunnel rotation - Value - 15 - - - Bits - 4 + NetName + IR_IE - + - Splitter + Tunnel rotation - Input Splitting - 16 - - - Output Splitting - 9, + NetName + CLK - + - Splitter + Tunnel - Input Splitting - 9,7 - - - Output Splitting - 16 + NetName + RW_IE - + - Ground + Tunnel - Bits - 7 + rotation + + + + NetName + RW_IE - + - Splitter + Tunnel - Input Splitting - 12,4 + rotation + - Output Splitting - 16 + NetName + CLK - + - Ground + atk16_regbank.dig + + + + + atk16_alu.dig - Bits - 4 + shapeType + SIMPLE + + + Label + ALU - + Driver - - rotation - - Bits 16 - - - - - Tunnel - - NetName - IR12_OE + flipSelPos + true - + Driver - - rotation - - Bits 16 @@ -1045,217 +738,234 @@ true - + Tunnel - - rotation - - NetName - IR9_OE + R2_OE - + - EEPROM + Driver - - Label - MEM_ROM - - - AddrBits - 15 - Bits 16 - - inverterConfig - - CS - - - + - Splitter + Tunnel - Input Splitting - 16 + rotation + - Output Splitting - 15,1 + NetName + ALU_OE - + - Demultiplexer + Tunnel - Bits - 15 + NetName + R1_OE - + - Ground + Probe - rotation - + Label + ALU - + - Driver + Counter - rotation - + valueIsProbe + true + + + Label + Microsequencer Bits - 16 + 3 - + Tunnel + + rotation + + NetName - MEM_OE + US_RS - + - Driver + VDD - Bits - 16 + rotation + - + - Clock - - - small - true - - - + Not + + Tunnel + + rotation + + NetName CLK - + - Tunnel + Reset - rotation - + invertOutput + false + + + + + Or + + + + + Tunnel + NetName - CLK + FLAG_EQ - + - Tunnel + Stop + + + + + Probe rotation - NetName - CLK + Label + OPCODE + + + intFormat + bin - + - Tunnel + Testcase - rotation - + Label + Sum program TODO - NetName - CLK + Testdata + + IN OUT + +program(0x4051, 0x40a2, 0x029b) + +0 x + - + - Tunnel + Out - rotation - + Label + OUT - NetName - CLK + Description + Dummy output - + - Tunnel + Ground rotation - + + + + + + In + - NetName - CLK + Label + IN - + - Tunnel + Ground rotation - - - - NetName - CLK + - + @@ -1264,136 +974,148 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + + + + + + + + + - + - - + + - - + + - - + + - - + + - - + + - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + + + + + @@ -1404,35 +1126,27 @@ - - - - - - - - - - + + - - + + - - + + - - + + - - + + - + @@ -1441,108 +1155,84 @@ - - - - - - - - - - - - - - - - - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - - - - - - @@ -1556,268 +1246,200 @@ - - + + - - - - + + + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + + + + + - - + + - - + + - - + + - - + + - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - + - - + + - - + + - - + + - - + + - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - + + - - + + diff --git a/digital/atk16_alu.dig b/digital/atk16_alu.dig index 09e0e1b..d456fee 100644 --- a/digital/atk16_alu.dig +++ b/digital/atk16_alu.dig @@ -333,21 +333,21 @@ 4 - + Splitter Input Splitting - 3 + 4 Output Splitting - 1*3 + 1*4 - + Splitter @@ -1122,60 +1122,64 @@ - Splitter + BarrelShifter - Input Splitting - 1*16 + Label + SRL - Output Splitting - 16 + Bits + 16 + + + direction + right - + - Tunnel + Demultiplexer - rotation - + Selector Bits + 3 - NetName - Y0 + Bits + 16 - + Tunnel rotation - + NetName - Y1 + A - + Tunnel rotation - + NetName - Y2 + B - + Tunnel @@ -1186,24 +1190,24 @@ NetName - Y3 + A - + - Tunnel + Splitter - rotation - + Input Splitting + 16 - NetName - Y4 + Output Splitting + 5, - + Tunnel @@ -1214,631 +1218,619 @@ NetName - Y5 + B - + - Tunnel + BarrelShifter - rotation - + Label + SRA - NetName - Y6 + Bits + 16 - - - - - Tunnel - - rotation - + barrelShifterMode + arithmetic - NetName - Y7 + direction + right - + - Tunnel + BarrelShifter - rotation - + Label + SLL - NetName - Y8 + Bits + 16 - + - Tunnel + Splitter - rotation - + Input Splitting + 1*4 - NetName - Y9 + Output Splitting + 4 - + - Tunnel + Out - rotation - + Label + FLAGS - NetName - Y10 + Bits + 4 - + - Tunnel + Splitter - rotation - + splitterSpreading + 2 - NetName - Y11 + Input Splitting + 16 + + + Output Splitting + 8*2 - + - Tunnel + BitSelector - rotation - - - - NetName - Y12 + Selector Bits + 4 - + - Tunnel + Const rotation - + - NetName - Y13 + Value + 15 + + + Bits + 4 - + - Tunnel + Splitter - rotation - + splitterSpreading + 2 - NetName - Y14 + Input Splitting + 8 + + + Output Splitting + 4*2 - + - Tunnel + Testcase - rotation - + Label + Add test 1 - NetName - Y15 + Testdata + + A B S FLAGS Y +0x1 0x2 3 0b0000 0x3 +0xff 0x1 3 0b0000 0x100 +0x1 0xffff 3 0b0101 0x0 + - + - BarrelShifter + Or - - Label - SRL - Bits - 16 - - - direction - right + 8 - + - Demultiplexer + Or Bits - 3 + 4 - + Splitter + + splitterSpreading + 2 + Input Splitting - 4 + 2 Output Splitting - 3,1 + 1*2 - + - Demultiplexer + Splitter - Selector Bits - 3 - - - Bits - 16 + splitterSpreading + 2 - - - - - Tunnel - - rotation - + Input Splitting + 4 - NetName - A + Output Splitting + 2*2 - + - Tunnel + Or - rotation - - - - NetName - B + Bits + 2 - + - Tunnel + NOr + + + + + Testcase - rotation - + Label + Sub test 1 - NetName - A + Testdata + + A B S FLAGS Y +0x10 0x1 2 0b0001 0xF +0x1 0x0 1 0b1000 0xFFFF + - + - Splitter + atk16_alu_carryfix.dig + + + + + Multiplexer - Input Splitting - 16 + flipSelPos + true - Output Splitting - 5, + Bits + 16 + + + Selector Bits + 2 - + - Tunnel + Ground rotation - + - NetName - B + Bits + 16 - + - Decoder + Splitter - Selector Bits - 3 + rotation + + + + Input Splitting + 1,1 + + + Output Splitting + 2 - + - Driver + Splitter - Bits - 16 + Input Splitting + 1*16 - flipSelPos - true + Output Splitting + 16 - + Tunnel rotation - + NetName - ALS_E + Y0 - + - Driver + Tunnel - Bits - 16 + rotation + - flipSelPos - true + NetName + Y1 - + Tunnel rotation - + NetName - ALS_E + Y2 - + - DriverInvSel + Tunnel - Bits - 16 + rotation + + + + NetName + Y3 - + - BarrelShifter + Tunnel - Label - SRA - - - Bits - 16 - - - barrelShifterMode - arithmetic + rotation + - direction - right + NetName + Y4 - + - Driver + Tunnel - Bits - 16 + rotation + - flipSelPos - true + NetName + Y5 - + - BarrelShifter + Tunnel - Label - SLL + rotation + - Bits - 16 + NetName + Y6 - + - Driver + Tunnel - Bits - 16 + rotation + - flipSelPos - true + NetName + Y7 - + - Splitter + Tunnel - Input Splitting - 1*4 + rotation + - Output Splitting - 4 + NetName + Y8 - + - Out + Tunnel - Label - FLAGS + rotation + - Bits - 4 + NetName + Y9 - + Tunnel + + rotation + + NetName - ALS_E + Y10 - + - Splitter + Tunnel - splitterSpreading - 2 - - - Input Splitting - 16 + rotation + - Output Splitting - 8*2 + NetName + Y11 - + - BitSelector + Tunnel - Selector Bits - 4 + rotation + + + + NetName + Y12 - + - Const + Tunnel rotation - - - - Value - 15 + - Bits - 4 + NetName + Y13 - + - Splitter + Tunnel - splitterSpreading - 2 - - - Input Splitting - 8 + rotation + - Output Splitting - 4*2 + NetName + Y14 - + - Testcase + Tunnel - Label - Add test 1 + rotation + - Testdata - - A B S FLAGS Y -0x1 0x2 3 0b0000 0x3 -0xff 0x1 3 0b0000 0x100 -0x1 0xffff 3 0b0101 0x0 - + NetName + Y15 - + - Or + Tunnel - Bits - 8 + NetName + ALU1 - + - Or + Multiplexer + + flipSelPos + true + Bits - 4 + 16 - + - Splitter + Tunnel - splitterSpreading - 2 - - - Input Splitting - 2 - - - Output Splitting - 1*2 + NetName + ALU2 - + - Splitter + Tunnel - splitterSpreading - 2 - - - Input Splitting - 4 + rotation + - Output Splitting - 2*2 + NetName + ALU1 - + - Or + Tunnel - Bits - 2 + rotation + + + + NetName + ALU2 - - - - NOr - - + - Testcase + Splitter - Label - Sub test 1 + rotation + - Testdata - - A B S FLAGS Y -0x10 0x1 2 0b0001 0xF -0x1 0x0 1 0b1000 0xFFFF - + Input Splitting + 1,1,1 + + + Output Splitting + 3 - - - - atk16_alu_carryfix.dig - - + @@ -1851,17 +1843,25 @@ - - + + - - + + + + + + + + + + @@ -1871,352 +1871,168 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -2231,8 +2047,28 @@ - - + + + + + + + + + + + + + + + + + + + + + + @@ -2243,16 +2079,24 @@ - - + + - - + + - - + + + + + + + + + + @@ -2264,6 +2108,14 @@ + + + + + + + + @@ -2278,25 +2130,65 @@ + + + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + + + + + + - - + + @@ -2318,6 +2210,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -2363,19 +2275,31 @@ - - + + + + + + - - + + - + - + + + + + + + + + @@ -2384,32 +2308,64 @@ - - - - - + - - + + - - + + + + + + + + + + + + + + - - + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2419,24 +2375,24 @@ - - + + - - + + - - + + - - + + - - + + @@ -2446,10 +2402,6 @@ - - - - @@ -2458,10 +2410,6 @@ - - - - @@ -2474,10 +2422,6 @@ - - - - @@ -2490,10 +2434,6 @@ - - - - @@ -2507,17 +2447,21 @@ - - + + - - + + + + + + @@ -2530,10 +2474,6 @@ - - - - @@ -2546,10 +2486,6 @@ - - - - @@ -2567,16 +2503,16 @@ - - + + - - + + - - + + @@ -2594,6 +2530,10 @@ + + + + @@ -2630,6 +2570,10 @@ + + + + @@ -2643,8 +2587,8 @@ - - + + diff --git a/digital/atk16_decoder.dig b/digital/atk16_decoder.dig new file mode 100644 index 0000000..ca22f72 --- /dev/null +++ b/digital/atk16_decoder.dig @@ -0,0 +1,402 @@ + + + 2 + + + + Out + + + Description + Write register selection + + + Label + RW_S + + + + + + Out + + + Description + Read register 1 selection + + + Label + R1_S + + + + + + Out + + + Description + Read register 2 selection + + + Label + R2_S + + + + + + Register + + + valueIsProbe + true + + + Label + IR + + + Bits + 16 + + + + + + In + + + Label + DBUS + + + Bits + 16 + + + isHighZ + true + + + + + + In + + + Description + Instruction register input enable + + + Label + IR_IE + + + + + + In + + + Label + CLK + + + + + + Splitter + + + splitterSpreading + 2 + + + Input Splitting + 16 + + + Output Splitting + 3,3,3,3,4 + + + + + + Splitter + + + Input Splitting + 9,7 + + + Output Splitting + 16 + + + + + + Ground + + + rotation + + + + Bits + 7 + + + + + + Tunnel + + + NetName + DBUS + + + + + + Tunnel + + + rotation + + + + NetName + DBUS + + + + + + Driver + + + Bits + 16 + + + flipSelPos + true + + + + + + Tunnel + + + NetName + DBUS + + + + + + Splitter + + + Input Splitting + 16 + + + Output Splitting + 3,9, + + + + + + Out + + + Description + ALU selection code + + + Label + ALU_S + + + Bits + 4 + + + + + + Splitter + + + Input Splitting + 3,1 + + + Output Splitting + 4 + + + + + + Splitter + + + Input Splitting + 4 + + + Output Splitting + 1,3 + + + + + + In + + + Description + Jump address output enable + + + Label + JA_OE + + + + + + Out + + + Description + Opcode + + + Label + OP + + + Bits + 4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/digital/atk16_mem.dig b/digital/atk16_mem.dig new file mode 100644 index 0000000..f323545 --- /dev/null +++ b/digital/atk16_mem.dig @@ -0,0 +1,461 @@ + + + 2 + + + + RAMAsync + + + AddrBits + 15 + + + Label + MEM_RAM + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + MEM_IE + + + + + + EEPROM + + + AddrBits + 15 + + + isProgramMemory + true + + + Label + MEM_ROM + + + Bits + 16 + + + Data + 4019,5200,8000,4051,40a2,29b,4014,2804,38c0,d9,40f2,4084,293,6500 +,4011,f000,4009,f000 + + + + + + Splitter + + + Input Splitting + 16 + + + Output Splitting + 15,1 + + + + + + Demultiplexer + + + Bits + 15 + + + + + + Ground + + + rotation + + + + + + + In + + + Description + Address + + + Label + ADDR + + + Bits + 16 + + + + + + In + + + Description + Data bus + + + Label + DBUS + + + Bits + 16 + + + isHighZ + true + + + + + + Driver + + + rotation + + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + MEM_OE + + + + + + In + + + Description + Memory input enable + + + Label + MEM_IE + + + + + + In + + + Description + Memory output enable + + + Label + MEM_OE + + + + + + Tunnel + + + NetName + MEM_OE + + + + + + Tunnel + + + NetName + MEM_IE + + + + + + Testcase + + + Testdata + + ADDR MEM_IE MEM_OE DBUS DBUS_out + +# read ROM +program(0xFF) +0x0 0 1 Z 0xFF + +# read RAM +memory MEM_RAM(0x0)=0x55; +0 0 0 Z X +0x8000 0 1 Z 0x55 + +# write to RAM +0x8000 1 0 0xAA 0xAA +0x8000 0 1 Z 0xAA + + + + + + + + Driver + + + Bits + 16 + + + + + + VDD + + + rotation + + + + + + + VDD + + + rotation + + + + + + + DriverInvSel + + + rotation + + + + Bits + 16 + + + flipSelPos + true + + + + + + Probe + + + Label + ROM_OUT + + + + + + Probe + + + Label + RAM_OUT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/digital/atk16_regbank.dig b/digital/atk16_regbank.dig new file mode 100644 index 0000000..35c072a --- /dev/null +++ b/digital/atk16_regbank.dig @@ -0,0 +1,1300 @@ + + + 2 + + + + In + + + Description + Data bus in + + + Label + Din + + + Bits + 16 + + + + + + Out + + + Description + Read register 1 data out + + + Label + D1 + + + Bits + 16 + + + + + + Out + + + Description + Read register 2 data out + + + Label + D2 + + + Bits + 16 + + + + + + Multiplexer + + + Selector Bits + 3 + + + Bits + 16 + + + + + + Ground + + + rotation + + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + Q1 + + + + + + Tunnel + + + rotation + + + + NetName + Q2 + + + + + + Tunnel + + + rotation + + + + NetName + Q3 + + + + + + Tunnel + + + rotation + + + + NetName + Q4 + + + + + + Tunnel + + + rotation + + + + NetName + Q5 + + + + + + Tunnel + + + rotation + + + + NetName + Q6 + + + + + + Ground + + + rotation + + + + Bits + 16 + + + + + + In + + + Description + Write register input enable + + + Label + RW_IE + + + + + + Multiplexer + + + Selector Bits + 3 + + + Bits + 16 + + + + + + Ground + + + rotation + + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + Q1 + + + + + + Tunnel + + + rotation + + + + NetName + Q2 + + + + + + Tunnel + + + rotation + + + + NetName + Q3 + + + + + + Tunnel + + + rotation + + + + NetName + Q4 + + + + + + Tunnel + + + rotation + + + + NetName + Q5 + + + + + + Tunnel + + + rotation + + + + NetName + Q6 + + + + + + Ground + + + rotation + + + + Bits + 16 + + + + + + In + + + Description + Write register select + + + Label + RW_S + + + Bits + 3 + + + + + + In + + + Description + Clock + + + Label + CLK + + + + + + In + + + Description + Read register 1 select + + + Label + R1_S + + + Bits + 3 + + + + + + Tunnel + + + NetName + Din + + + + + + Tunnel + + + NetName + RW_IE + + + + + + Register + + + valueIsProbe + true + + + Label + RA + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + Din + + + + + + Tunnel + + + rotation + + + + NetName + CLK + + + + + + Tunnel + + + NetName + Q1 + + + + + + And + + + + + Tunnel + + + rotation + + + + NetName + RW_IE + + + + + + Tunnel + + + rotation + + + + NetName + RW_A + + + + + + Register + + + valueIsProbe + true + + + Label + RB + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + Din + + + + + + Tunnel + + + rotation + + + + NetName + CLK + + + + + + Tunnel + + + NetName + Q2 + + + + + + And + + + + + Tunnel + + + rotation + + + + NetName + RW_IE + + + + + + Tunnel + + + rotation + + + + NetName + RW_B + + + + + + Register + + + valueIsProbe + true + + + Label + RC + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + Din + + + + + + Tunnel + + + rotation + + + + NetName + CLK + + + + + + Tunnel + + + NetName + Q3 + + + + + + And + + + + + Register + + + valueIsProbe + true + + + Label + RD + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + Din + + + + + + Tunnel + + + rotation + + + + NetName + CLK + + + + + + Tunnel + + + NetName + Q4 + + + + + + And + + + + + Tunnel + + + rotation + + + + NetName + RW_IE + + + + + + Tunnel + + + rotation + + + + NetName + RW_D + + + + + + Register + + + valueIsProbe + true + + + Label + PA + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + Din + + + + + + Tunnel + + + rotation + + + + NetName + CLK + + + + + + Tunnel + + + NetName + Q5 + + + + + + And + + + + + Tunnel + + + rotation + + + + NetName + RW_IE + + + + + + Tunnel + + + rotation + + + + NetName + RW_PA + + + + + + Register + + + valueIsProbe + true + + + Label + PB + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + Din + + + + + + Tunnel + + + rotation + + + + NetName + CLK + + + + + + Tunnel + + + NetName + Q6 + + + + + + And + + + + + Tunnel + + + rotation + + + + NetName + RW_IE + + + + + + Tunnel + + + rotation + + + + NetName + RW_PB + + + + + + Ground + + + rotation + + + + Bits + 16 + + + + + + Ground + + + rotation + + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + RW_IE + + + + + + Tunnel + + + rotation + + + + NetName + RW_C + + + + + + Decoder + + + Selector Bits + 3 + + + + + + In + + + Description + Read register 2 select + + + Label + R2_S + + + Bits + 3 + + + + + + Tunnel + + + NetName + CLK + + + + + + Tunnel + + + NetName + RW_A + + + + + + Tunnel + + + NetName + RW_B + + + + + + Tunnel + + + NetName + RW_C + + + + + + Tunnel + + + NetName + RW_D + + + + + + Tunnel + + + NetName + RW_PA + + + + + + Tunnel + + + NetName + RW_PB + + + + + + Testcase + + + Testdata + + CLK Din RW_IE RW_S R1_S R2_S D1 D2 +# store and read from RA works +C 0xF 1 1 0 X X X +C 0 0 0 1 X 0xF X +C 0x5 1 1 1 X 0x5 X +C 0 0 0 1 X 0x5 X + +# zero register read and write +C 0xA 1 0 0 X 0 X + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/high-level-lang-idea.perl b/high-level-lang-idea.perl new file mode 100644 index 0000000..426cae8 --- /dev/null +++ b/high-level-lang-idea.perl @@ -0,0 +1,36 @@ +# Builtin types: +# u8, u16, i8, i16, block[T], void + +# allocate 16 words, returning block +# a block is similar to a C pointer but contains the allocated size as well +decl v :: block[u16] = alloc-words 16 + +# define a fn that zeroes a block of memory +decl zero-block :: block[u16] -> void +func zero-block block + # for each address in block + for-addr addr block + # store the value 0 in memory at address addr + store addr 0 + +# call fn zero-block in inlined mode +zero-block% v + +# compute first 16 fibonacci numbers +decl a :: u16 = 0 +decl b :: u16 = 1 +for-index idx block + # declarations in loop constructs are hoisted + decl addr :: u16 = addr-at idx block + decl v :: u16 + + if idx == 0 + v = a + else if idx == 1 + v = b + else + v = a + b + + store addr v + a = b + b = v diff --git a/src/assembler.py b/src/assembler.py index 9e2d92f..5802983 100755 --- a/src/assembler.py +++ b/src/assembler.py @@ -45,7 +45,7 @@ def parse(line: str) -> list[str]: def eval_expr(expr: str) -> int: expr = eval_symbol(expr) - return eval(expr, labels) # eval as Python expr + return eval(expr, labels.copy()) # eval as Python expr def eval_symbol(c: str): if c in labels: @@ -85,7 +85,7 @@ labels: dict[str, int] = {} address = 0 for (lineNo, line) in enumerate(src_lines): - line = line.strip() + line = line.split(";")[0].strip() if line == "": continue keyword, *args = line.lower().split() match keyword: @@ -98,8 +98,6 @@ for (lineNo, line) in enumerate(src_lines): address += 1 -print("labels:", labels) - # 2nd pass address = 0 @@ -122,33 +120,50 @@ for (lineNo, line) in enumerate(src_lines): # Instructions case "alu": + # S (alu op) + # L (lhs) + # R (rhs) + # T (target) word = (0b0000 << 12) + \ - (eval_expr(args[0]) << 9) + \ - (eval_expr(args[1]) << 6) + \ - (eval_expr(args[2]) << 3) + \ + (eval_expr(args[0]) << 3) + \ + (eval_expr(args[1]) << 9) + \ + (eval_expr(args[2]) << 6) + \ (eval_expr(args[3]) << 0) case "als": + # S (alu op) + # L (lhs) + # R (rhs) + # T (target) word = (0b0001 << 12) + \ - (eval_expr(args[0]) << 9) + \ - (eval_expr(args[1]) << 6) + \ - (eval_expr(args[2]) << 3) + \ + (eval_expr(args[0]) << 3) + \ + (eval_expr(args[1]) << 9) + \ + (eval_expr(args[2]) << 6) + \ (eval_expr(args[3]) << 0) case "ldr": + # R (address) + # T (target) word = (0b0010 << 12) + \ (eval_expr(args[0]) << 9) + \ - (eval_expr(args[1]) << 6) + (eval_expr(args[1]) << 0) case "str": + # R (address) + # T (value to store) word = (0b0011 << 12) + \ (eval_expr(args[0]) << 9) + \ (eval_expr(args[1]) << 6) case "ldi": + # T (target) + # I (immediate) word = (0b0100 << 12) + \ - (eval_expr(args[0]) << 9) + \ - (eval_expr(args[1]) << 0) + (eval_expr(args[0]) << 0) + \ + (eval_expr(args[1]) << 3) case "jmp": + # R (reg holding address) word = (0b0101 << 12) + \ (eval_expr(args[0]) << 9) case "br": + # F (flag selector) + # R (reg holding address) word = (0b0110 << 12) + \ (eval_expr(args[0]) << 9) + \ (eval_expr(args[1]) << 6) @@ -160,20 +175,20 @@ for (lineNo, line) in enumerate(src_lines): word = (0b0000 << 12) + \ (eval_expr(args[0]) << 9) + \ (eval_expr(args[1]) << 6) + \ - (eval_expr(args[2]) << 3) + \ - (eval_expr("al_a_plus_b") << 0) + (eval_expr("al_a_plus_b") << 3) + \ + (eval_expr(args[2]) << 0) case "sub": word = (0b0000 << 12) + \ (eval_expr(args[0]) << 9) + \ (eval_expr(args[1]) << 6) + \ - (eval_expr(args[2]) << 3) + \ - (eval_expr("al_a_minus_b") << 0) + (eval_expr("al_a_minus_b") << 3) + \ + (eval_expr(args[2]) << 0) case "mov": word = (0b0000 << 12) + \ (eval_expr("rz") << 9) + \ (eval_expr(args[0]) << 6) + \ - (eval_expr(args[1]) << 3) + \ - (eval_expr("al_a_plus_b") << 0) + (eval_expr("al_a_plus_b") << 3) + \ + (eval_expr(args[1]) << 0) # Default case: evaluate as is (e.g. data word) case _: @@ -185,6 +200,10 @@ for (lineNo, line) in enumerate(src_lines): if len(result) < 2 * address + 1: result.extend((2 * address + 1 - len(result)) * nop) + for (label, label_addr) in labels.items(): + if address == label_addr: + print(f"{label}:") + print(f"{address:>08x} 0x{word:>04x} {line}") result[2 * address + 0] = ((word >> 8) & 0xff) result[2 * address + 1] = ((word >> 0) & 0xff) diff --git a/src/test.atk16 b/src/test.atk16 index 399bd7e..364480b 100644 --- a/src/test.atk16 +++ b/src/test.atk16 @@ -10,7 +10,7 @@ @label program ldi RA 10 ; RA := 10 - ldi RB 20 ; RB := 10 + ldi RB 20 ; RB := 20 add RA RB RC ; RC := RA + RB ldi RD ram_offset ; store address of ram_offset in RD ldr RD RD ; dereference ram_offset address diff --git a/src/test_sum.atk16 b/src/test_sum.atk16 new file mode 100644 index 0000000..3f69a55 --- /dev/null +++ b/src/test_sum.atk16 @@ -0,0 +1,3 @@ + ldi RA 10 ; RA := 10 + ldi RB 20 ; RB := 20 + add RA RB RC ; RC := RA + RB diff --git a/src/ucode.py b/src/ucode.py index ea5c040..9d7c55c 100755 --- a/src/ucode.py +++ b/src/ucode.py @@ -16,16 +16,16 @@ PC_CO = 0b0000_0000_0000_0001 PC_IE = 0b0000_0000_0000_0010 PC_OE = 0b0000_0000_0000_0100 MAR_IE = 0b0000_0000_0000_1000 -RAM_IE = 0b0000_0000_0001_0000 -RAM_OE = 0b0000_0000_0010_0000 -R1_IE = 0b0000_0000_0100_0000 +MEM_IE = 0b0000_0000_0001_0000 +MEM_OE = 0b0000_0000_0010_0000 +RW_IE = 0b0000_0000_0100_0000 R1_OE = 0b0000_0000_1000_0000 -R2_IE = 0b0000_0001_0000_0000 -R2_OE = 0b0000_0010_0000_0000 -IR_IE = 0b0000_0100_0000_0000 -L9_OE = 0b0000_1000_0000_0000 -L12_OE = 0b0001_0000_0000_0000 -ALU_OE = 0b0010_0000_0000_0000 +R2_OE = 0b0000_0001_0000_0000 +IR_IE = 0b0000_0010_0000_0000 +L9_OE = 0b0000_0100_0000_0000 +unused1 = 0b0000_1000_0000_0000 +ALU_OE = 0b0001_0000_0000_0000 +FR_IE = 0b0010_0000_0000_0000 HALT = 0b0100_0000_0000_0000 US_RS = 0b1000_0000_0000_0000 @@ -39,22 +39,22 @@ def not_branch(bs): def branch(false_branch, true_branch): return [false_branch, true_branch] -fetch = [PC_OE|MAR_IE, RAM_OE|IR_IE|PC_CO] +fetch = [PC_OE|MAR_IE, MEM_OE|IR_IE|PC_CO] def nop(): return not_branch([*fetch, US_RS, 0, 0, 0, 0, 0]) ucode = [ - # ALU 0000 LLLR RRTT TSSS - not_branch([*fetch, ALU_OE, US_RS, 0, 0, 0, 0]), - # ALS 0001 LLLR RRTT TSSS - not_branch([*fetch, ALU_OE, US_RS, 0, 0, 0, 0]), - # LDR 0010 RRRT TTXX XXXX - not_branch([*fetch, R1_OE|MAR_IE, RAM_OE|R2_IE, US_RS, 0, 0, 0]), + # ALU 0000 LLLR RRSS STTT + not_branch([*fetch, ALU_OE|FR_IE|RW_IE, US_RS, 0, 0, 0, 0]), + # ALS 0001 LLLR RRSS STTT + not_branch([*fetch, ALU_OE|FR_IE|RW_IE, US_RS, 0, 0, 0, 0]), + # LDR 0010 RRRX XXXX XTTT + not_branch([*fetch, R1_OE|MAR_IE, MEM_OE|RW_IE, US_RS, 0, 0, 0]), # STR 0011 RRRT TTXX XXXX - not_branch([*fetch, R1_OE|MAR_IE, R2_OE|RAM_IE, US_RS, 0, 0, 0]), - # LDI 0100 RRRI IIII IIII - not_branch([*fetch, L9_OE|R1_IE, US_RS, 0, 0, 0, 0]), + not_branch([*fetch, R1_OE|MAR_IE, R2_OE|MEM_IE, US_RS, 0, 0, 0]), + # LDI 0100 IIII IIII ITTT + not_branch([*fetch, H9_OE|RW_IE, US_RS, 0, 0, 0, 0]), # JMP 0101 RRRX XXXX XXXX not_branch([*fetch, R1_OE|PC_IE, US_RS, 0, 0, 0, 0]), # BR 0110 XFFR RRXX XXXX -- cgit v1.3