From 5b6637fb92c54b8f367ec8751f53f6f238d8dbed Mon Sep 17 00:00:00 2001 From: Jan Tuomi Date: Sun, 9 Apr 2023 18:26:25 +0300 Subject: Remake ALU --- digital/atk16.dig | 1080 +++++++++++--------- digital/atk16_alu.dig | 2290 +++++++++++++----------------------------- digital/atk16_alu_fo.dig | 494 +++++++++ digital/atk16_alu_fz.dig | 192 ++++ digital/atk16_alu_inputs.dig | 237 +++++ digital/atk16_decoder.dig | 306 +++--- digital/atk16_jump_unit.dig | 216 ++++ digital/atk16_mem.dig | 17 +- digital/atk16_regbank.dig | 262 +++-- digital/tests_alu.dig | 26 - src/assembler.py | 341 ++++--- src/test.atk16 | 2 +- src/test_fibo.atk16 | 47 + src/ucode.py | 41 +- 14 files changed, 3015 insertions(+), 2536 deletions(-) create mode 100644 digital/atk16_alu_fo.dig create mode 100644 digital/atk16_alu_fz.dig create mode 100644 digital/atk16_alu_inputs.dig create mode 100644 digital/atk16_jump_unit.dig delete mode 100644 digital/tests_alu.dig create mode 100644 src/test_fibo.atk16 diff --git a/digital/atk16.dig b/digital/atk16.dig index 15912d7..2716409 100644 --- a/digital/atk16.dig +++ b/digital/atk16.dig @@ -2,6 +2,12 @@ 2 + + romContent + + + + view1 @@ -41,6 +47,10 @@ + + showDataTable + true + @@ -145,36 +155,6 @@ - - EEPROM - - - AddrBits - 8 - - - Label - UCODE - - - Bits - 16 - - - Data - c,221,3040,8000,4*0,c,221,3040,8000,4*0,c,221,3040,8000,4*0,c -,221,3040,8000,4*0,c,221,88,60,8000,0,0,0,c,221,88,60,8000,0,0,0 -,c,221,88,110,8000,0,0,0,c,221,88,110,8000,0,0,0,c,221,440,8000 -,4*0,c,221,440,8000,4*0,c,221,82,8000,4*0,c,221,82,8000,4*0,c -,221,8000,5*0,c,221,102,8000,4*0,c,221,8000,5*0,c,221,8000,5*0 -,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c -,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221 -,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000 -,5*0,c,221,8000,5*0,c,221,4000,5*0,c,221,4000 - - - - Splitter @@ -185,16 +165,6 @@ - - VDD - - - rotation - - - - - Tunnel @@ -209,16 +179,6 @@ - - Ground - - - rotation - - - - - BitSelector @@ -261,34 +221,6 @@ - - VDD - - - rotation - - - - - - - Splitter - - - mirror - true - - - Input Splitting - 16 - - - Output Splitting - 1*16 - - - - CounterPreset @@ -326,7 +258,7 @@ rotation - + @@ -345,136 +277,6 @@ - - Tunnel - - - NetName - PC_CO - - - - - - Tunnel - - - NetName - PC_IE - - - - - - Tunnel - - - NetName - PC_OE - - - - - - Tunnel - - - NetName - MAR_IE - - - - - - Tunnel - - - NetName - MEM_IE - - - - - - Tunnel - - - NetName - MEM_OE - - - - - - Tunnel - - - NetName - R1_OE - - - - - - Tunnel - - - NetName - R2_OE - - - - - - Tunnel - - - NetName - IR_IE - - - - - - Tunnel - - - NetName - JA_OE - - - - - - Tunnel - - - NetName - ALU_OE - - - - - - Tunnel - - - NetName - US_RS - - - - - - Tunnel - - - NetName - FR_IE - - - - Clock @@ -598,20 +400,24 @@ shapeType - SIMPLE + CUSTOM - + Tunnel + + rotation + + NetName - OPCODE + RW_IE - + Tunnel @@ -622,24 +428,33 @@ NetName - JA_OE + CLK - + - Tunnel + atk16_regbank.dig + + + + + Counter - rotation - + valueIsProbe + true - NetName - IR_IE + Label + Microsequencer + + + Bits + 3 - + Tunnel @@ -650,20 +465,25 @@ NetName - CLK + US_RS - + - Tunnel + VDD - NetName - RW_IE + rotation + - + + + + Not + + Tunnel @@ -674,157 +494,310 @@ NetName - RW_IE + CLK - + - Tunnel + Reset - rotation - - - - NetName - CLK + invertOutput + false - + - atk16_regbank.dig + Or - + - atk16_alu.dig + Tunnel - shapeType - SIMPLE + NetName + FLAG_EQ + + + + + + Out + + + Description + Dummy output Label - ALU + OUT - + - Driver + Ground - Bits - 16 + rotation + + + + + + In + - flipSelPos - true + Label + IN - + - Driver + Ground - Bits - 16 + rotation + + + + + + + Tunnel + + + rotation + - flipSelPos + NetName + IR_IE + + + + + + Tunnel + + + rotation + + + + NetName + CLK + + + + + + Tunnel + + + NetName + OPCODE + + + + + + Splitter + + + mirror true + + Input Splitting + 16 + + + Output Splitting + 1*16 + - + Tunnel NetName - R2_OE + PC_CO - + - Driver + Tunnel - Bits - 16 + NetName + PC_IE - + Tunnel - rotation - + NetName + PC_OE + + + + + Tunnel + NetName - ALU_OE + MAR_IE - + Tunnel NetName - R1_OE + MEM_IE - + - Probe + Tunnel - Label - ALU + NetName + MEM_OE - + - Counter + Tunnel - valueIsProbe - true + NetName + R1_OE + + + + + Tunnel + - Label - Microsequencer + NetName + R2_OE + + + + + Tunnel + - Bits - 3 + NetName + IR_IE - + Tunnel - rotation - + NetName + ALU_OE + + + + + Tunnel + NetName US_RS - + + + + Tunnel + + + NetName + FR_IE + + + + + + Tunnel + + + NetName + RW_IE + + + + + + Stop + + + + + Tunnel + + + NetName + LI_OE + + + + + + EEPROM + + + AddrBits + 8 + + + Label + UCODE + + + Bits + 16 + + + Data + c,221,3040,8000,4*0,c,221,3040,8000,4*0,c,221,3040,8000,4*0,c +,221,3040,8000,4*0,c,221,88,60,8000,0,0,0,c,221,88,60,8000,0,0,0 +,c,221,88,90,8000,0,0,0,c,221,88,90,8000,0,0,0,c,221,840,8000 +,4*0,c,221,840,8000,4*0,c,221,82,8000,4*0,c,221,82,8000,4*0,c +,221,802,8000,4*0,c,221,802,8000,4*0,c,221,8000,5*0,c,221,82,8000 +,4*0,c,221,8000,5*0,c,221,802,8000,4*0,c,221,8000,5*0,c,221,8000 +,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0 +,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c +,221,8000,5*0,c,221,8000,5*0,c,221,4000,5*0,c,221,4000 + + + VDD @@ -834,12 +807,27 @@ - + - Not - - + Ground + + + rotation + + + + + + + VDD + + + rotation + + + + Tunnel @@ -850,58 +838,101 @@ NetName - CLK + LI_OE - + - Reset + atk16_alu.dig - invertOutput - false + shapeType + SIMPLE + + + Label + ALU - + - Or + atk16_alu_inputs.dig - + + + + Driver + + + Bits + 16 + + + + + + Driver + + + Bits + 16 + + + flipSelPos + true + + + + + + Driver + + + Bits + 16 + + + flipSelPos + true + + + Tunnel NetName - FLAG_EQ + R1_OE - + - Stop - - + Tunnel + + + NetName + R2_OE + + + - Probe + Tunnel rotation - Label + NetName OPCODE - - intFormat - bin - - + Testcase @@ -921,51 +952,74 @@ program(0x4051, 0x40a2, 0x029b) - + - Out + atk16_jump_unit.dig + + + + + Tunnel - Label - OUT + rotation + - Description - Dummy output + NetName + OPCODE - + - Ground + Tunnel rotation + + NetName + ALU_OE + - + - In + Probe Label - IN + PC - + - Ground + Tunnel rotation - + + + + NetName + OPCODE - + + + + Probe + + + Label + OPCODE + + + @@ -974,32 +1028,40 @@ program(0x4051, 0x40a2, 0x029b) - - + + - - + + - - + + - + - + - - + + + + + + - - + + + + + + @@ -1009,6 +1071,10 @@ program(0x4051, 0x40a2, 0x029b) + + + + @@ -1026,60 +1092,64 @@ program(0x4051, 0x40a2, 0x029b) - - + + + + + + - + - - - - - - + + - - + + - - + + + + + + - + - - + + - + - - + + - - + + @@ -1087,51 +1157,63 @@ program(0x4051, 0x40a2, 0x029b) - + - - + + - - + + - - + + - - + + - - + + + + + + + + + + - - + + - - + + - - + + - - + + - - + + + + + + @@ -1150,93 +1232,93 @@ program(0x4051, 0x40a2, 0x029b) - - + + + + + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - - @@ -1246,8 +1328,12 @@ program(0x4051, 0x40a2, 0x029b) - - + + + + + + @@ -1262,12 +1348,12 @@ program(0x4051, 0x40a2, 0x029b) - - + + - - + + @@ -1277,69 +1363,77 @@ program(0x4051, 0x40a2, 0x029b) + + + + - - + + - - + + - - + + - - + + + + + + - - + + - + - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -1347,20 +1441,28 @@ program(0x4051, 0x40a2, 0x029b) - + - - + + + + + + - - + + + + + + @@ -1374,56 +1476,60 @@ program(0x4051, 0x40a2, 0x029b) - - + + - - - - - - + + + + + + - + - - + + - - + + - - + + - - + + - - + + - - + + + + + + @@ -1434,17 +1540,37 @@ program(0x4051, 0x40a2, 0x029b) - - + + - - + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/digital/atk16_alu.dig b/digital/atk16_alu.dig index d456fee..0f40f94 100644 --- a/digital/atk16_alu.dig +++ b/digital/atk16_alu.dig @@ -1,641 +1,706 @@ 2 - + + + romContent + + + + + + Width + 5 + + - 74382.dig - - - - - 74382.dig - - - - - 74382.dig - - - - - 74382.dig - - - - - VDD + Add - rotation - + Label + PLUS - - - - - VDD - - rotation - + Bits + 16 - + - VDD + Tunnel rotation - + - - - - - VDD - - rotation - + NetName + A - + - Ground + Tunnel rotation - + + + + NetName + B - + Ground + + + + + Tunnel - rotation - + NetName + Y - + - Ground + Tunnel - rotation - + NetName + FC - + - Ground + Driver - rotation - + Bits + 16 - + - Splitter + Tunnel - mirror - true - - - Input Splitting - 16 + rotation + - Output Splitting - 1*16 + NetName + S0 - + - In + Driver + + + + + Tunnel - Description - LHS of binary ALU operation - - - Label - A + rotation + - Bits - 16 + NetName + S0 - + - In + atk16_alu_fo.dig - - Description - RHS of binary ALU operation - Label - B - - - Bits - 16 + Overflow flag - + Tunnel + + rotation + + NetName - A0 + A - + Tunnel + + rotation + + NetName - A1 + B - + + + + Ground + + Tunnel NetName - A2 + Y - + Tunnel NetName - A3 + FC - + - Tunnel + Driver - NetName - A4 + Bits + 16 - + Tunnel + + rotation + + NetName - A5 + S1 - + + + + Driver + + Tunnel + + rotation + + NetName - A6 + S1 - + - Tunnel + Sub - NetName - A7 + Label + MINUS + + + Bits + 16 - + - Tunnel + And - NetName - A8 + Bits + 16 - + - Tunnel + Text - NetName - A9 + Description + AND - + Tunnel + + rotation + + NetName - A10 + A - + Tunnel + + rotation + + NetName - A11 + B - + - Tunnel + Driver - NetName - A12 + Bits + 16 - + Tunnel + + rotation + + NetName - A13 + S2 - + Tunnel NetName - A14 + Y - + - Tunnel + Or - NetName - A15 + Bits + 16 - + - In + Text Description - ALU operation code - - - Label - S - - - Bits - 4 + OR - + - Splitter + Tunnel - Input Splitting - 4 + rotation + - Output Splitting - 1*4 + NetName + A - + - Splitter + Tunnel - mirror - true - - - Input Splitting - 16 + rotation + - Output Splitting - 1*16 + NetName + B - + - Tunnel + Driver - NetName - B0 + Bits + 16 - + Tunnel + + rotation + + NetName - B1 + S3 - + Tunnel NetName - B2 + Y - + - Tunnel + XOr - NetName - B3 + Bits + 16 - + - Tunnel + Text - NetName - B4 + Description + XOR - + Tunnel + + rotation + + NetName - B5 + A - + Tunnel + + rotation + + NetName - B6 + B - + - Tunnel + Driver - NetName - B7 + Bits + 16 - + Tunnel + + rotation + + NetName - B8 + S4 - + Tunnel NetName - B9 + Y - + - Tunnel + BarrelShifter - NetName - B10 + Label + LOG SHIFT RIGHT + + + Bits + 16 + + + direction + right - + Tunnel + + rotation + + NetName - B11 + A - + Tunnel + + rotation + + NetName - B12 + B_L5 - + - Tunnel + Driver - NetName - B13 + Bits + 16 - + Tunnel + + rotation + + NetName - B14 + S5 - + Tunnel NetName - B15 + Y - + - Tunnel + BarrelShifter - rotation - + Label + ARI SHIFT RIGHT - NetName - A0 + Bits + 16 + + + barrelShifterMode + arithmetic + + + direction + right - + Tunnel rotation - + NetName - A1 + A + + + + + + Driver + + + Bits + 16 - + Tunnel + + rotation + + NetName - A2 + S6 - + Tunnel NetName - A3 + Y - + - Tunnel + BarrelShifter - rotation - + Label + LOG SHIFT LEFT - NetName - B0 + Bits + 16 - + Tunnel rotation - + NetName - B1 + A - + - Tunnel + Driver - NetName - B2 + Bits + 16 - + Tunnel + + rotation + + NetName - B3 + S7 - + Tunnel - - rotation - - NetName - Y0 + Y - + Tunnel @@ -646,30 +711,38 @@ NetName - Y1 + B_L5 - + Tunnel + + rotation + + NetName - Y2 + B_L5 - + Tunnel + + rotation + + NetName - Y3 + B15 - + Tunnel @@ -680,10 +753,10 @@ NetName - Y4 + Y15 - + Tunnel @@ -694,30 +767,30 @@ NetName - Y5 + A15 - + Tunnel NetName - Y6 + FO - + - Tunnel + Text - NetName - Y7 + Description + Sign flag - + Tunnel @@ -728,58 +801,54 @@ NetName - Y8 + Y15 - + Tunnel - - rotation - - NetName - Y9 + FS - + - Tunnel + atk16_alu_fz.dig - NetName - Y10 + Label + Zero flag - + Tunnel + + rotation + + NetName - Y11 + Y - + Tunnel - - rotation - - NetName - Y12 + FZ - + Tunnel @@ -790,325 +859,361 @@ NetName - Y13 + S1 - + - Tunnel + Testcase - NetName - Y14 + Label + PLUS test + + + Testdata + + A B S FLAGS Y +0x1 0x2 0 0b0000 0x3 +0xff 0x1 0 0b0000 0x100 +0x1 0xffff 0 0b0101 0x0 +0x4000 0x4000 0 0b1010 0x8000 + - + - Tunnel + Testcase - NetName - Y15 + Label + MINUS test + + + Testdata + + A B S FLAGS Y +0x10 0x1 1 0b0000 0xF +0x1 0x0 1 0b0000 0x1 +0x0 0x1 1 0b1001 0xFFFF +0x8000 0x1 1 0b0010 0x7FFF + - + - Tunnel + In - rotation - + Description + LHS of binary ALU operation - NetName - A4 + Label + A + + + Bits + 16 - + - Tunnel + In - rotation - + Description + RHS of binary ALU operation - NetName - A5 + Label + B + + + Bits + 16 - + - Tunnel + In - NetName - A6 + Description + ALU operation code + + + Label + S + + + Bits + 3 - + - Tunnel + Text - NetName - A7 + Description + S Y +0 A + B +1 A - B +2 A and B +3 A or B +4 A xor B +5 A >> B # logical +6 A >>> B # arithmetic +7 A << B - + - Tunnel + Decoder - rotation - + Selector Bits + 3 - NetName - A8 + flipSelPos + true - + Tunnel - - rotation - - NetName - A9 + S0 - + Tunnel NetName - A10 + S1 - + Tunnel NetName - A11 + S2 - + Tunnel - - rotation - - NetName - A12 + S3 - + Tunnel - - rotation - - NetName - A13 + S4 - + Tunnel NetName - A14 + S5 - + Tunnel NetName - A15 + S6 - + Tunnel - - rotation - - NetName - B4 + S7 - + Tunnel rotation - + NetName - B5 + A - + - Tunnel + Splitter - NetName - B6 + Input Splitting + 16 + + + Output Splitting + 15,1 - + Tunnel + + rotation + + NetName - B7 + B - + - Tunnel + Splitter - rotation - + Input Splitting + 16 - NetName - B8 + Output Splitting + 15,1 - + - Tunnel + Splitter - rotation - + Input Splitting + 16 - NetName - B9 + Output Splitting + 5 - + Tunnel NetName - B10 + B_L5 - + Tunnel NetName - B11 + A15 - + Tunnel - - rotation - - NetName - B12 + B15 - + - Tunnel + Splitter - rotation - + Input Splitting + 16 - NetName - B13 + Output Splitting + 15,1 - + Tunnel + + rotation + + NetName - B14 + Y - + Tunnel NetName - B15 + Y15 - + Out Description - ALU output + Output Label @@ -1119,67 +1224,63 @@ 16 - + - BarrelShifter + Splitter - Label - SRL - - - Bits - 16 + Input Splitting + 1*4 - direction - right + Output Splitting + 4 - + - Demultiplexer + Out - Selector Bits - 3 + Label + FLAGS Bits - 16 + 4 - + Tunnel rotation - + NetName - A + FO - + Tunnel rotation - + NetName - B + FZ - + Tunnel @@ -1190,1405 +1291,404 @@ NetName - A + FS - + - Splitter + Tunnel - Input Splitting - 16 + rotation + - Output Splitting - 5, + NetName + FC - + - Tunnel + PullDown rotation - - NetName - B - - - - - - BarrelShifter - - - Label - SRA - - - Bits - 16 - - - barrelShifterMode - arithmetic - - - direction - right - - - - - - BarrelShifter - - - Label - SLL - - - Bits - 16 - - - - - - Splitter - - - Input Splitting - 1*4 - - - Output Splitting - 4 - - - - - - Out - - - Label - FLAGS - - - Bits - 4 - - - - - - Splitter - - - splitterSpreading - 2 - - - Input Splitting - 16 - - - Output Splitting - 8*2 - - - - - - BitSelector - - - Selector Bits - 4 - - - - - - Const - - - rotation - - - - Value - 15 - - - Bits - 4 - - - - - - Splitter - - - splitterSpreading - 2 - - - Input Splitting - 8 - - - Output Splitting - 4*2 - - - - - - Testcase - - - Label - Add test 1 - - - Testdata - - A B S FLAGS Y -0x1 0x2 3 0b0000 0x3 -0xff 0x1 3 0b0000 0x100 -0x1 0xffff 3 0b0101 0x0 - - - - - - - Or - - - Bits - 8 - - - - - - Or - - - Bits - 4 - - - - - - Splitter - - - splitterSpreading - 2 - - - Input Splitting - 2 - - - Output Splitting - 1*2 - - - - - - Splitter - - - splitterSpreading - 2 - - - Input Splitting - 4 - - - Output Splitting - 2*2 - - - - - - Or - - - Bits - 2 - - - - - - NOr - - - - - Testcase - - - Label - Sub test 1 - - - Testdata - - A B S FLAGS Y -0x10 0x1 2 0b0001 0xF -0x1 0x0 1 0b1000 0xFFFF - - - - - - - atk16_alu_carryfix.dig - - - - - Multiplexer - - - flipSelPos - true - - - Bits - 16 - - - Selector Bits - 2 - - - - - - Ground - - - rotation - - - - Bits - 16 - - - - - - Splitter - - - rotation - - - - Input Splitting - 1,1 - - - Output Splitting - 2 - - - - - - Splitter - - - Input Splitting - 1*16 - - - Output Splitting - 16 - - - - - - Tunnel - - - rotation - - - - NetName - Y0 - - - - - - Tunnel - - - rotation - - - - NetName - Y1 - - - - - - Tunnel - - - rotation - - - - NetName - Y2 - - - - - - Tunnel - - - rotation - - - - NetName - Y3 - - - - - - Tunnel - - - rotation - - - - NetName - Y4 - - - - - - Tunnel - - - rotation - - - - NetName - Y5 - - - - - - Tunnel - - - rotation - - - - NetName - Y6 - - - - - - Tunnel - - - rotation - - - - NetName - Y7 - - - - - - Tunnel - - - rotation - - - - NetName - Y8 - - - - - - Tunnel - - - rotation - - - - NetName - Y9 - - - - - - Tunnel - - - rotation - - - - NetName - Y10 - - - - - - Tunnel - - - rotation - - - - NetName - Y11 - - - - - - Tunnel - - - rotation - - - - NetName - Y12 - - - - - - Tunnel - - - rotation - - - - NetName - Y13 - - - - - - Tunnel - - - rotation - - - - NetName - Y14 - - - - - - Tunnel - - - rotation - - - - NetName - Y15 - - - - - - Tunnel - - - NetName - ALU1 - - - - - - Multiplexer - - - flipSelPos - true - - - Bits - 16 - - - - - - Tunnel - - - NetName - ALU2 - - - - - - Tunnel - - - rotation - - - - NetName - ALU1 - - - - - - Tunnel - - - rotation - - - - NetName - ALU2 - - - - - - Splitter - - - rotation - - - - Input Splitting - 1,1,1 - - - Output Splitting - 3 - - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - + - - - - - - - - - - + + - - + + - - - - - - - - - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - + + - + - - - - - - - - - - + + - - + + - - + + - - + + - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + diff --git a/digital/atk16_alu_fo.dig b/digital/atk16_alu_fo.dig new file mode 100644 index 0000000..ecf0021 --- /dev/null +++ b/digital/atk16_alu_fo.dig @@ -0,0 +1,494 @@ + + + 2 + + + Label + alu_fo + + + romContent + + + + + + Width + 4 + + + + + Testcase + + + Testdata + + A15 B15 Y15 ~A/S FO +0 0 0 0 0 +0 0 1 0 1 +0 1 0 0 0 +0 1 1 0 0 +1 0 0 0 0 +1 0 1 0 0 +1 1 0 0 1 +1 1 1 0 0 +0 0 0 1 0 +0 0 1 1 0 +0 1 0 1 0 +0 1 1 1 1 +1 0 0 1 1 +1 0 1 1 0 +1 1 0 1 0 +1 1 1 1 0 + + + + + + + + Out + + + Label + FO + + + Inputs + 1 + + + + + + Or + + + wideShape + true + + + Inputs + 4 + + + + + + And + + + wideShape + true + + + Inputs + 4 + + + + + + And + + + wideShape + true + + + Inputs + 4 + + + + + + And + + + wideShape + true + + + Inputs + 4 + + + + + + And + + + wideShape + true + + + Inputs + 4 + + + + + + In + + + rotation + + + + Label + ~A/S + + + + + + Not + + + rotation + + + + + + + In + + + rotation + + + + Label + A15 + + + + + + Not + + + rotation + + + + + + + In + + + rotation + + + + Label + B15 + + + + + + Not + + + rotation + + + + + + + In + + + rotation + + + + Label + Y15 + + + + + + Not + + + rotation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/digital/atk16_alu_fz.dig b/digital/atk16_alu_fz.dig new file mode 100644 index 0000000..2da652a --- /dev/null +++ b/digital/atk16_alu_fz.dig @@ -0,0 +1,192 @@ + + + 2 + + + Label + alu_fz + + + romContent + + + + + + + + In + + + Label + Y + + + Bits + 16 + + + + + + Splitter + + + Input Splitting + 16 + + + Output Splitting + 4*4 + + + + + + Splitter + + + Input Splitting + 4 + + + Output Splitting + 1*4 + + + + + + Out + + + Label + FZ + + + + + + Testcase + + + Testdata + + Y FZ +0x0 1 +0x1 0 +0xff 0 + + + + + + + NOr + + + Inputs + 4 + + + + + + Or + + + Bits + 4 + + + Inputs + 4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/digital/atk16_alu_inputs.dig b/digital/atk16_alu_inputs.dig new file mode 100644 index 0000000..2ed5b74 --- /dev/null +++ b/digital/atk16_alu_inputs.dig @@ -0,0 +1,237 @@ + + + 2 + + + Description + Maps the R1 input to the A output. Uses OPCODE parity to mux either the R2 input (even parity) or the RW_S input, here acting as a small immediate value, to the B output. + + + romContent + + + + + + Width + 5 + + + + + In + + + Description + Register 1 value from regbank + + + Label + R1 + + + Bits + 16 + + + + + + In + + + Description + Register 2 value from regbank + + + Label + R2 + + + Bits + 16 + + + + + + Splitter + + + Input Splitting + 4 + + + Output Splitting + 1 + + + + + + Multiplexer + + + Bits + 16 + + + + + + In + + + Description + Register 2 selector + + + Label + R2_S + + + Bits + 3 + + + + + + In + + + Description + Opcode + + + Label + OPCODE + + + Bits + 4 + + + + + + Out + + + Description + Output A + + + Label + A + + + Bits + 16 + + + + + + Out + + + Description + Output B + + + Label + B + + + Bits + 16 + + + + + + Splitter + + + Input Splitting + 3,13 + + + Output Splitting + 16 + + + + + + Ground + + + Bits + 13 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/digital/atk16_decoder.dig b/digital/atk16_decoder.dig index ca22f72..0570615 100644 --- a/digital/atk16_decoder.dig +++ b/digital/atk16_decoder.dig @@ -1,50 +1,19 @@ 2 - + + + romContent + + + + + + Width + 5 + + - - Out - - - Description - Write register selection - - - Label - RW_S - - - - - - Out - - - Description - Read register 1 selection - - - Label - R1_S - - - - - - Out - - - Description - Read register 2 selection - - - Label - R2_S - - - - Register @@ -123,34 +92,6 @@ - - Splitter - - - Input Splitting - 9,7 - - - Output Splitting - 16 - - - - - - Ground - - - rotation - - - - Bits - 7 - - - - Tunnel @@ -176,120 +117,187 @@ - Driver + Out + + Description + Opcode + + + Label + OP + Bits - 16 + 4 + + + + + Out + - flipSelPos - true + Description + Write register selection + + + Label + RW_S + + + Bits + 3 - + - Tunnel + Out - NetName - DBUS + Description + ALU selection code + + + Label + ALU_S + + + Bits + 3 - + - Splitter + Out - Input Splitting - 16 + Description + Read register 1 selection - Output Splitting - 3,9, + Label + R1_S + + + Bits + 3 - + Out Description - ALU selection code + Read register 2 selection Label - ALU_S + R2_S Bits - 4 + 3 - + Splitter Input Splitting - 3,1 + 16 Output Splitting - 4 + 9, - + - Splitter + Driver - Input Splitting - 4 + Bits + 16 - Output Splitting - 1,3 + flipSelPos + true + + + + + + Tunnel + + + NetName + DBUS - + In Description - Jump address output enable + Low 9 bits immediate value output enable Label - JA_OE + LI_OE - + - Out + Splitter - Description - Opcode + Input Splitting + 9,7 - Label - OP + Output Splitting + 16 + + + + + + Ground + + + rotation + Bits - 4 + 7 + + + + + + Testcase + + + Testdata + + CLK DBUS IR_IE LI_OE OP RW_S R1_S R2_S ALU_S +C 0b0000001010011000 1 0 0 1 2 3 0 + - + @@ -299,71 +307,51 @@ - - - - - - - - - - - - - + - - - - - - - - - - - - - - - - - + - + - + - - + + - - + + - - + + + + + + + + + + @@ -374,28 +362,24 @@ - - + + - - - - - - + + - - + + - - + + - - + + diff --git a/digital/atk16_jump_unit.dig b/digital/atk16_jump_unit.dig new file mode 100644 index 0000000..1156aae --- /dev/null +++ b/digital/atk16_jump_unit.dig @@ -0,0 +1,216 @@ + + + 2 + + + Description + Uses OPCODE parity to choose between relative addressing mode (even parity) or absolute addressing mode (odd parity). + + + romContent + + + + + + Width + 5 + + + + + In + + + Description + Jump address + + + Label + ADDR + + + Bits + 16 + + + + + + In + + + Description + PC value + + + Label + PC + + + Bits + 16 + + + + + + In + + + Description + OPCODE + + + Label + OPCODE + + + Bits + 4 + + + + + + Splitter + + + Input Splitting + 4 + + + Output Splitting + 1, + + + + + + Text + + + Description + OP parity bit + + + + + + Out + + + Description + Result PC value + + + Label + PC_RES + + + Bits + 16 + + + + + + Add + + + Bits + 16 + + + + + + Multiplexer + + + Bits + 16 + + + + + + Ground + + + + + Testcase + + + Testdata + + PC ADDR OPCODE PC_RES +10 20 0b0101 20 +10 20 0b0110 30 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/digital/atk16_mem.dig b/digital/atk16_mem.dig index f323545..c5ce679 100644 --- a/digital/atk16_mem.dig +++ b/digital/atk16_mem.dig @@ -1,7 +1,18 @@ 2 - + + + romContent + + + + + + Width + 5 + + RAMAsync @@ -56,8 +67,8 @@ Data - 4019,5200,8000,4051,40a2,29b,4014,2804,38c0,d9,40f2,4084,293,6500 -,4011,f000,4009,f000 + 4203,5040,8000,420a,4414,650,4802,2900,38c0,12c0,441e,4810,651 +,7500,4202,f000,4201,f000 diff --git a/digital/atk16_regbank.dig b/digital/atk16_regbank.dig index 35c072a..d65e6fb 100644 --- a/digital/atk16_regbank.dig +++ b/digital/atk16_regbank.dig @@ -1,7 +1,18 @@ 2 - + + + romContent + + + + + + Width + 5 + + In @@ -169,20 +180,6 @@ - - Ground - - - rotation - - - - Bits - 16 - - - - In @@ -309,20 +306,6 @@ - - Ground - - - rotation - - - - Bits - 16 - - - - In @@ -505,7 +488,7 @@ rotation - + NetName @@ -519,7 +502,7 @@ rotation - + NetName @@ -548,7 +531,7 @@ rotation - + NetName @@ -594,7 +577,7 @@ rotation - + NetName @@ -608,7 +591,7 @@ rotation - + NetName @@ -655,7 +638,7 @@ rotation - + NetName @@ -669,7 +652,7 @@ rotation - + NetName @@ -698,7 +681,7 @@ rotation - + NetName @@ -730,7 +713,7 @@ Label - PA + RE Bits @@ -805,7 +788,7 @@ NetName - RW_PA + RW_E @@ -819,7 +802,7 @@ Label - PB + RF Bits @@ -833,7 +816,7 @@ rotation - + NetName @@ -847,7 +830,7 @@ rotation - + NetName @@ -876,7 +859,7 @@ rotation - + NetName @@ -894,39 +877,11 @@ NetName - RW_PB + RW_F - - Ground - - - rotation - - - - Bits - 16 - - - - - - Ground - - - rotation - - - - Bits - 16 - - - - Tunnel @@ -1038,7 +993,7 @@ NetName - RW_PA + RW_E @@ -1048,7 +1003,7 @@ NetName - RW_PB + RW_F @@ -1073,6 +1028,133 @@ C 0xA 1 0 0 X 0 X + + Register + + + valueIsProbe + true + + + Label + RG + + + Bits + 16 + + + + + + Tunnel + + + rotation + + + + NetName + Din + + + + + + Tunnel + + + rotation + + + + NetName + CLK + + + + + + Tunnel + + + NetName + Q7 + + + + + + And + + + + + Tunnel + + + rotation + + + + NetName + RW_IE + + + + + + Tunnel + + + rotation + + + + NetName + RW_G + + + + + + Tunnel + + + rotation + + + + NetName + Q7 + + + + + + Tunnel + + + rotation + + + + NetName + Q7 + + + + + + Tunnel + + + NetName + RW_G + + + + @@ -1107,14 +1189,14 @@ C 0xA 1 0 0 X 0 X - - - - + + + + @@ -1123,6 +1205,10 @@ C 0xA 1 0 0 X 0 X + + + + @@ -1163,10 +1249,6 @@ C 0xA 1 0 0 X 0 X - - - - @@ -1179,6 +1261,10 @@ C 0xA 1 0 0 X 0 X + + + + @@ -1227,6 +1313,10 @@ C 0xA 1 0 0 X 0 X + + + + @@ -1235,10 +1325,6 @@ C 0xA 1 0 0 X 0 X - - - - @@ -1292,8 +1378,8 @@ C 0xA 1 0 0 X 0 X - - + + diff --git a/digital/tests_alu.dig b/digital/tests_alu.dig deleted file mode 100644 index 9390503..0000000 --- a/digital/tests_alu.dig +++ /dev/null @@ -1,26 +0,0 @@ - - - 2 - - - - Testcase - - - Label - test01 - - - Testdata - - A B Y -0 0 1 - - - - - - - - - \ No newline at end of file diff --git a/src/assembler.py b/src/assembler.py index 5802983..7deb0f0 100755 --- a/src/assembler.py +++ b/src/assembler.py @@ -25,8 +25,8 @@ src_lines = src.splitlines() def parse(line: str) -> list[str]: depth = 0 - result = [] - acc = "" + result: list[str] = [] + acc: str = "" for c in line: if c.isspace() and depth == 0: result.append(acc) @@ -47,42 +47,47 @@ def eval_expr(expr: str) -> int: expr = eval_symbol(expr) return eval(expr, labels.copy()) # eval as Python expr +constants: dict[str, str] = { + # Registers + "rz": "0", + "ra": "1", + "rb": "2", + "rc": "3", + "rd": "4", + "rf": "5", + "rg": "6", + # ALU instructions + "al_plus": "0", + "al_minus": "1", + "al_and": "2", + "al_or": "3", + "al_xor": "4", + "al_shift_lr": "5", + "al_shift_ar": "6", + "al_shift_ll": "7", + # ALU flags + "f_carry": "0", + "f_overflow": "1", + "f_zero": "2", + "f_sign": "3", +} + def eval_symbol(c: str): if c in labels: return str(labels[c]) - match c: - # Registers - case "rz": return "0" - case "ra": return "1" - case "rb": return "2" - case "rc": return "3" - case "rd": return "4" - case "pa": return "5" - case "pb": return "6" - # ALU instructions - case "al_clear": return "0" - case "al_b_minus_a": return "1" - case "al_a_minus_b": return "2" - case "al_a_plus_b": return "3" - case "al_a_xor_b": return "4" - case "al_a_or_b": return "5" - case "al_a_and_b": return "6" - case "al_preset": return "7" - case "al_logical_shift_right": return "8" - case "al_arithmetic_shift_right": return "9" - case "al_logical_shift_left": return "10" - # ALU flags - case "f_carry": return "0" - case "f_overflow": return "1" - case "f_zero": return "2" - case "f_sign": return "3" - case _: return c - -# 1st pass, gather labels + if c in constants: + return constants[c] + + return c + +# 1st pass, gather labels, set options +options: dict[str, str] = { + "stack_pointer": "6" # RG +} labels: dict[str, int] = {} -address = 0 +address: int = 0 for (lineNo, line) in enumerate(src_lines): line = line.split(";")[0].strip() @@ -95,11 +100,116 @@ for (lineNo, line) in enumerate(src_lines): case "@label": labels[args[0]] = address continue + case "@opt": + opt_name = args[0] + opt_value = constants.get(args[1], args[1]) + options[opt_name] = opt_value + case _: + pass address += 1 # 2nd pass +def make_alr(alu_op: str, left: str, right: str, target: str) -> list[int]: + """ALR 0000 TTTL LLRR RSSS""" + target_e = eval_expr(target) + left_e = eval_expr(left) + right_e = eval_expr(right) + alu_op_e = eval_expr(alu_op) + word = (0b0000 << 12) + \ + (target_e << 9) + \ + (left_e << 6) + \ + (right_e << 3) + \ + alu_op_e + return [word] + +def make_ali(alu_op: str, left: str, imm: str, target: str) -> list[int]: + """ALI 0001 TTTL LLII ISSS""" + target_e = eval_expr(target) + left_e = eval_expr(left) + imm_e = eval_expr(imm) + alu_op_e = eval_expr(alu_op) + word = (0b0001 << 12) + \ + (target_e << 9) + \ + (left_e << 6) + \ + (imm_e << 3) + \ + alu_op_e + return [word] + +def make_ldr(to_reg: str, addr_reg: str) -> list[int]: + """LDR 0010 TTTR RRXX XXXX""" + to_reg_e = eval_expr(to_reg) + addr_reg_e = eval_expr(addr_reg) + word = (0b0010 << 12) + \ + (to_reg_e << 9) + \ + (addr_reg_e << 6) + return [word] + +def make_str(from_reg: str, addr_reg: str) -> list[int]: + """STR 0011 TTTR RRXX XXXX""" + from_reg_e = eval_expr(from_reg) + addr_reg_e = eval_expr(addr_reg) + word = (0b0011 << 12) + \ + (from_reg_e << 9) + \ + (addr_reg_e << 6) + return [word] + +def make_ldi(to_reg: str, imm: str) -> list[int]: + """LDI 0100 TTTI IIII IIII""" + to_reg_e = eval_expr(to_reg) + imm_e = eval_expr(imm) + word = (0b0100 << 12) + \ + (to_reg_e << 9) + \ + imm_e + return [word] + +def make_jpr(addr_reg: str) -> list[int]: + """JPR 0101 XXXR RRXX XXXX""" + addr_reg_e = eval_expr(addr_reg) + word = (0b0101 << 12) + \ + (addr_reg_e << 6) + return [word] + +def make_jpi(address: int, imm: str) -> list[int]: + """JPI 0110 XXXI IIII IIII""" + imm_e = eval_expr(imm) + imm_e -= address + word = (0b0110 << 12) + \ + imm_e + return [word] + +def make_br(flag_s: str, addr_reg: str) -> list[int]: + """BR 0111 XFFR RRXX XXXX""" + flag_s_e = eval_expr(flag_s) + addr_reg_e = eval_expr(addr_reg) + word = (0b0111 << 12) + \ + (flag_s_e << 9) + \ + (addr_reg_e << 6) + return [word] + +def make_bri(address: int, flag_s: str, imm: str) -> list[int]: + """BRI 1000 XFFI IIII IIII""" + flag_s_e = eval_expr(flag_s) + imm_e = eval_expr(imm) + imm_e -= address + word = (0b1000 << 12) + \ + (flag_s_e << 9) + \ + imm_e + return [word] + +def make_hlt() -> list[int]: + """HLT 1111 XXXX XXXX XXXX""" + word = (0b1111 << 12) + return [word] + +# def make_spu(reg: str) -> list[int]: +# stack_pointer = options["stack_pointer"] +# reg = eval_symbol(reg) +# words_inc: list[int] = make_inc(stack_pointer, stack_pointer) +# words_str: list[int] = make_str(reg, stack_pointer) +# return words_inc + words_str + address = 0 nop = bytearray([0b1000_0000, 0]) result = bytearray() @@ -115,85 +225,52 @@ for (lineNo, line) in enumerate(src_lines): case "@address": address = eval_expr(args[0]) continue - case "@label": + case "@label" | "@opt": continue # Instructions - case "alu": - # S (alu op) - # L (lhs) - # R (rhs) - # T (target) - word = (0b0000 << 12) + \ - (eval_expr(args[0]) << 3) + \ - (eval_expr(args[1]) << 9) + \ - (eval_expr(args[2]) << 6) + \ - (eval_expr(args[3]) << 0) - case "als": - # S (alu op) - # L (lhs) - # R (rhs) - # T (target) - word = (0b0001 << 12) + \ - (eval_expr(args[0]) << 3) + \ - (eval_expr(args[1]) << 9) + \ - (eval_expr(args[2]) << 6) + \ - (eval_expr(args[3]) << 0) + case "alr": + words = make_alr(*args) + case "ali": + words = make_ali(*args) case "ldr": - # R (address) - # T (target) - word = (0b0010 << 12) + \ - (eval_expr(args[0]) << 9) + \ - (eval_expr(args[1]) << 0) + words = make_ldr(*args) case "str": - # R (address) - # T (value to store) - word = (0b0011 << 12) + \ - (eval_expr(args[0]) << 9) + \ - (eval_expr(args[1]) << 6) + words = make_str(*args) case "ldi": - # T (target) - # I (immediate) - word = (0b0100 << 12) + \ - (eval_expr(args[0]) << 0) + \ - (eval_expr(args[1]) << 3) - case "jmp": - # R (reg holding address) - word = (0b0101 << 12) + \ - (eval_expr(args[0]) << 9) + words = make_ldi(*args) + case "jpr": + words = make_jpr(*args) + case "jpi": + words = make_jpi(address, *args) case "br": - # F (flag selector) - # R (reg holding address) - word = (0b0110 << 12) + \ - (eval_expr(args[0]) << 9) + \ - (eval_expr(args[1]) << 6) + words = make_br(*args) + case "bri": + words = make_bri(address, *args) case "hlt": - word = 0b1111 << 12 + words = make_hlt() # Pseudoinstructions case "add": - word = (0b0000 << 12) + \ - (eval_expr(args[0]) << 9) + \ - (eval_expr(args[1]) << 6) + \ - (eval_expr("al_a_plus_b") << 3) + \ - (eval_expr(args[2]) << 0) + words = make_alr("al_plus", *args) case "sub": - word = (0b0000 << 12) + \ - (eval_expr(args[0]) << 9) + \ - (eval_expr(args[1]) << 6) + \ - (eval_expr("al_a_minus_b") << 3) + \ - (eval_expr(args[2]) << 0) + words = make_alr("al_minus", *args) + case "inc": + words = make_ali("al_plus", args[0], "1", args[0]) + case "dec": + words = make_ali("al_minus", args[0], "1", args[0]) case "mov": - word = (0b0000 << 12) + \ - (eval_expr("rz") << 9) + \ - (eval_expr(args[0]) << 6) + \ - (eval_expr("al_a_plus_b") << 3) + \ - (eval_expr(args[1]) << 0) + words = make_ali("al_plus", args[0], "0", args[1]) + # case "csr": + # reg = args[0] + # words_spu = make_spu(reg) + # words = [] + # # todo finish this # Default case: evaluate as is (e.g. data word) case _: try: - word = eval_expr(keyword) + words = [eval_expr(keyword)] except: raise Exception(f"Invalid assembly at {infile_path}:{lineNo + 1}\n\n{line}") @@ -204,79 +281,13 @@ for (lineNo, line) in enumerate(src_lines): if address == label_addr: print(f"{label}:") - print(f"{address:>08x} 0x{word:>04x} {line}") - result[2 * address + 0] = ((word >> 8) & 0xff) - result[2 * address + 1] = ((word >> 0) & 0xff) - address += 1 + for word in words: + print(f"{address:>08x} 0x{word:>04x} {line}") + result[2 * address + 0] = ((word >> 8) & 0xff) + result[2 * address + 1] = ((word >> 0) & 0xff) + address += 1 with open(outfile_path, "wb") as f: f.write(result) print(f"Wrote {len(result)} bytes to {outfile_path}") - -with open(f"{outfile_path}.logisim.txt", "w") as f: - f.write("v2.0 raw\n") - run_length = 0 - run_last = "" - for i in range(len(result) // 2): - b0 = result[2 * i + 0] - b1 = result[2 * i + 1] - word = f"{b0:>02x}{b1:>02x}\n" - - if word != run_last and run_length <= 1: - f.write(f"{run_last}") - run_length = 1 - run_last = word - elif word != run_last and run_length > 1: - f.write(f"{run_length}*{run_last}") - run_length = 1 - run_last = word - else: - run_length += 1 - - if run_length <= 1: - f.write(f"{run_last}") - else: - f.write(f"{run_length}*{run_last}") - -print(f"Wrote Logisim image format to {outfile_path}.logisim.txt") - -with open(f"{outfile_path}.ver.txt", "w") as f: - f.write("addr/data: 15 16") - run_length = 0 - run_last = "" - written = -1 - - def update_layout(): - if run_last == "": return - if written % 8 == 0: - f.write("\n") - else: - f.write(" ") - - for i in range(len(result) // 2): - b0 = result[2 * i + 0] - b1 = result[2 * i + 1] - word = f"{b0:>02x}{b1:>02x}" - - if word != run_last and run_length <= 1: - f.write(f"{run_last}") - run_length = 1 - run_last = word - written += 1 - update_layout() - elif word != run_last and run_length > 1: - f.write(f"{run_length}*{run_last}") - run_length = 1 - run_last = word - written += 1 - update_layout() - else: - run_length += 1 - - if run_length <= 1: - f.write(f"{run_last}") - else: - f.write(f"{run_length}*{run_last}") - -print(f"Wrote verification test format to {outfile_path}.ver.txt") diff --git a/src/test.atk16 b/src/test.atk16 index 364480b..da7c7c8 100644 --- a/src/test.atk16 +++ b/src/test.atk16 @@ -3,7 +3,7 @@ ; ROM (and program execution) starts at offset 0x0 @address 0x0 ldi RA program - jmp RA + jpr RA @label ram_offset 0x8000 ; store ram offset for later memory access diff --git a/src/test_fibo.atk16 b/src/test_fibo.atk16 new file mode 100644 index 0000000..7f1abb9 --- /dev/null +++ b/src/test_fibo.atk16 @@ -0,0 +1,47 @@ +@opt stack_pointer RG + +@label program + ; call fibo subroutine with parameter 10 + ldi RA 10 + csr fibo + hlt + +@label fibo + ; function fibo + ; parameters: + ; RA n : u16 + ; return value: + ; RA fibo(n) : u16 + + spu RB ; prelude + spu RC + + ldi RC 2 ; if n < 2, return n + sub RA RC RA + bri f_sign fibo_early + + spu RD ; prelude + spu RE + + ldi RE 1 ; constant 1 + ldi RB 0 ; a = 0 + ldi RC 1 ; b = 1 +@label fibo_loop + add RB RC RD ; v = a + b + mov RC RB ; a = b + mov RD RC ; b = v + sub RA RE RA ; n -= 1 + bri f_zero fibo_done ; loop while n > 0 + jpi fibo_loop + +@label fibo_early + spo RC + spo RB + rsr +@label fibo_done + ldr RD RA + spo RE + spo RD + spo RC + spo RB + rsr diff --git a/src/ucode.py b/src/ucode.py index 9d7c55c..3c34a71 100755 --- a/src/ucode.py +++ b/src/ucode.py @@ -20,23 +20,23 @@ MEM_IE = 0b0000_0000_0001_0000 MEM_OE = 0b0000_0000_0010_0000 RW_IE = 0b0000_0000_0100_0000 R1_OE = 0b0000_0000_1000_0000 -R2_OE = 0b0000_0001_0000_0000 +R2_OE = 0b0000_0001_0000_0000 # needed? IR_IE = 0b0000_0010_0000_0000 -L9_OE = 0b0000_0100_0000_0000 -unused1 = 0b0000_1000_0000_0000 +unused = 0b0000_0100_0000_0000 +LI_OE = 0b0000_1000_0000_0000 ALU_OE = 0b0001_0000_0000_0000 FR_IE = 0b0010_0000_0000_0000 HALT = 0b0100_0000_0000_0000 US_RS = 0b1000_0000_0000_0000 BRANCH_FLAG_STATES_N = 2 -UCODE_N = 2**3 +UCODE_N: int = 2**3 CONTROL_WORD_SIZE = 2 -def not_branch(bs): +def not_branch(bs: list[int]) -> list[list[int]]: return BRANCH_FLAG_STATES_N * [bs] -def branch(false_branch, true_branch): +def branch(false_branch: list[int], true_branch: list[int]) -> list[list[int]]: return [false_branch, true_branch] fetch = [PC_OE|MAR_IE, MEM_OE|IR_IE|PC_CO] @@ -45,25 +45,26 @@ def nop(): return not_branch([*fetch, US_RS, 0, 0, 0, 0, 0]) ucode = [ - # ALU 0000 LLLR RRSS STTT + # ALR 0000 TTTL LLRR RSSS not_branch([*fetch, ALU_OE|FR_IE|RW_IE, US_RS, 0, 0, 0, 0]), - # ALS 0001 LLLR RRSS STTT + # ALI 0001 TTTL LLII ISSS not_branch([*fetch, ALU_OE|FR_IE|RW_IE, US_RS, 0, 0, 0, 0]), - # LDR 0010 RRRX XXXX XTTT + # LDR 0010 TTTR RRXX XXXX not_branch([*fetch, R1_OE|MAR_IE, MEM_OE|RW_IE, US_RS, 0, 0, 0]), - # STR 0011 RRRT TTXX XXXX - not_branch([*fetch, R1_OE|MAR_IE, R2_OE|MEM_IE, US_RS, 0, 0, 0]), - # LDI 0100 IIII IIII ITTT - not_branch([*fetch, H9_OE|RW_IE, US_RS, 0, 0, 0, 0]), - # JMP 0101 RRRX XXXX XXXX + # STR 0011 TTTR RRXX XXXX + not_branch([*fetch, R1_OE|MAR_IE, R1_OE|MEM_IE, US_RS, 0, 0, 0]), + # LDI 0100 TTTI IIII IIII + not_branch([*fetch, LI_OE|RW_IE, US_RS, 0, 0, 0, 0]), + # JPR 0101 XXXR RRXX XXXX not_branch([*fetch, R1_OE|PC_IE, US_RS, 0, 0, 0, 0]), - # BR 0110 XFFR RRXX XXXX + # JPI 0110 XXXI IIII IIII + not_branch([*fetch, LI_OE|PC_IE, US_RS, 0, 0, 0, 0]), + # BR 0111 XFFR RRXX XXXX branch([*fetch, US_RS, 0, 0, 0, 0, 0], - [*fetch, R2_OE|PC_IE, US_RS, 0, 0, 0, 0]), - # NOP 0111 XXXX XXXX XXXX - nop(), - # NOP 1000 XXXX XXXX XXXX - nop(), + [*fetch, R1_OE|PC_IE, US_RS, 0, 0, 0, 0]), + # BRI 1000 XFFI IIII IIII + branch([*fetch, US_RS, 0, 0, 0, 0, 0], + [*fetch, LI_OE|PC_IE, US_RS, 0, 0, 0, 0]), # NOP 1001 XXXX XXXX XXXX nop(), # NOP 1010 XXXX XXXX XXXX -- cgit v1.3