From da14e7ca7f31cb4b9a975dbe349fb4d385592b9c Mon Sep 17 00:00:00 2001 From: Jan Tuomi Date: Tue, 11 Apr 2023 14:05:41 +0300 Subject: Fix bugs --- digital/atk16.dig | 446 ++++++++++++++++------------ digital/atk16_decoder.dig | 44 +-- digital/atk16_mem.dig | 8 +- digital/atk16_regbank.dig | 723 +++++++++++++++++++++++++++------------------- src/asm_pass2.py | 8 +- src/asm_pass3.py | 2 + src/asm_pass4.py | 6 + src/assembler.py | 5 +- src/assembler_eval.py | 24 +- src/assembler_ops.py | 16 +- src/ext_std.py | 19 +- src/test.atk16 | 2 +- src/test_fibo.atk16 | 72 +++-- src/ucode.py | 8 +- 14 files changed, 792 insertions(+), 591 deletions(-) diff --git a/digital/atk16.dig b/digital/atk16.dig index 1345925..ca4aa6d 100644 --- a/digital/atk16.dig +++ b/digital/atk16.dig @@ -277,34 +277,6 @@ - - Clock - - - small - true - - - runRealTime - true - - - Frequency - 10 - - - - - - Tunnel - - - NetName - CLK - - - - Tunnel @@ -390,11 +362,6 @@ - - Break - - - atk16_decoder.dig @@ -524,50 +491,6 @@ - - Out - - - Description - Dummy output - - - Label - OUT - - - - - - Ground - - - rotation - - - - - - - In - - - Label - IN - - - - - - Ground - - - rotation - - - - - Tunnel @@ -694,16 +617,6 @@ - - Tunnel - - - NetName - IM_M - - - - Tunnel @@ -786,12 +699,12 @@ Data - c,221,3040,8000,4*0,c,221,3040,8000,4*0,c,221,3140,8000,4*0,c -,221,3140,8000,4*0,c,221,88,60,8000,0,0,0,c,221,88,60,8000,0,0,0 -,c,221,88,90,8000,0,0,0,c,221,88,90,8000,0,0,0,c,221,840,8000 + c,221,3040,8000,4*0,c,221,3040,8000,4*0,c,221,3440,8000,4*0,c +,221,3440,8000,4*0,c,221,88,60,8000,0,0,0,c,221,88,60,8000,0,0,0 +,c,221,88,110,8000,0,0,0,c,221,88,110,8000,0,0,0,c,221,840,8000 ,4*0,c,221,840,8000,4*0,c,221,82,8000,4*0,c,221,82,8000,4*0,c -,221,902,8000,4*0,c,221,902,8000,4*0,c,221,8000,5*0,c,221,82,8000 -,4*0,c,221,8000,5*0,c,221,902,8000,4*0,c,221,44,8000,4*0,c,221 +,221,c02,8000,4*0,c,221,c02,8000,4*0,c,221,8000,5*0,c,221,82,8000 +,4*0,c,221,8000,5*0,c,221,c02,8000,4*0,c,221,44,8000,4*0,c,221 ,44,8000,4*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221 ,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,8000 ,5*0,c,221,8000,5*0,c,221,8000,5*0,c,221,4000,5*0,c,221,4000 @@ -910,26 +823,6 @@ - - Testcase - - - Label - Sum program TODO - - - Testdata - - IN OUT - -program(0x4051, 0x40a2, 0x029b) - -0 x - - - - - atk16_jump_unit.dig @@ -997,6 +890,147 @@ program(0x4051, 0x40a2, 0x029b) + + Tunnel + + + NetName + IM_M + + + + + + Tunnel + + + NetName + R2_OE + + + + + + Driver + + + Bits + 16 + + + flipSelPos + true + + + + + + Tunnel + + + NetName + R2_OE + + + + + + Testcase + + + Label + Sum program TODO + + + Testdata + + IN OUT + +program(0x4051, 0x40a2, 0x029b) + +0 x + + + + + + + Out + + + Description + Dummy output + + + Label + OUT + + + + + + Ground + + + rotation + + + + + + + In + + + Label + IN + + + + + + Ground + + + rotation + + + + + + + Clock + + + small + true + + + runRealTime + true + + + Frequency + 50 + + + + + + Tunnel + + + NetName + CLK + + + + + + Break + + + @@ -1059,10 +1093,6 @@ program(0x4051, 0x40a2, 0x029b) - - - - @@ -1075,10 +1105,6 @@ program(0x4051, 0x40a2, 0x029b) - - - - @@ -1115,6 +1141,10 @@ program(0x4051, 0x40a2, 0x029b) + + + + @@ -1149,12 +1179,20 @@ program(0x4051, 0x40a2, 0x029b) + + + + + + + + @@ -1231,6 +1269,10 @@ program(0x4051, 0x40a2, 0x029b) + + + + @@ -1243,13 +1285,21 @@ program(0x4051, 0x40a2, 0x029b) + + + + + + + + - - + + @@ -1353,8 +1403,16 @@ program(0x4051, 0x40a2, 0x029b) + + + + + + + + @@ -1388,140 +1446,148 @@ program(0x4051, 0x40a2, 0x029b) - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + + + + + + + + + diff --git a/digital/atk16_decoder.dig b/digital/atk16_decoder.dig index 0570615..b8eb088 100644 --- a/digital/atk16_decoder.dig +++ b/digital/atk16_decoder.dig @@ -258,34 +258,6 @@ - - Splitter - - - Input Splitting - 9,7 - - - Output Splitting - 16 - - - - - - Ground - - - rotation - - - - Bits - 7 - - - - Testcase @@ -299,6 +271,16 @@ C 0b0000001010011000 1 0 0 1 2 3 0 + + BitExtender + + + inputBits + 9 + + + + @@ -347,7 +329,7 @@ C 0b0000001010011000 1 0 0 1 2 3 0 - + @@ -361,10 +343,6 @@ C 0b0000001010011000 1 0 0 1 2 3 0 - - - - diff --git a/digital/atk16_mem.dig b/digital/atk16_mem.dig index 0a1b0e8..15f080d 100644 --- a/digital/atk16_mem.dig +++ b/digital/atk16_mem.dig @@ -67,10 +67,10 @@ Data - 420a,9c00,3dc0,1fc8,6004,f000,35c0,1fc8,37c0,1fc8,4602,259,8609 -,39c0,1fc8,3bc0,1fc8,4a01,4400,4601,898,14c0,1700,269,8400,5ff6 -,1fc9,27c0,1fc9,25c0,1fc9,2dc0,5180,2840,1fc9,2bc0,1fc9,29c0,1fc9 -,27c0,1fc9,25c0,1fc9,2dc0,5180 + 6001,8000,4001,2a00,400a,9e00,1fe0,3178,1b48,6001,f000,3148,1b48 +,3150,1b48,1011,860a,3158,1b48,4200,4401,650,1280,14c0,1009,8408 +,61fa,1b49,2540,1b49,2340,1b49,2f40,51c0,10c0,1b49,2740,1b49,2540 +,1b49,2340,1b49,2f40,51c0 diff --git a/digital/atk16_regbank.dig b/digital/atk16_regbank.dig index d65e6fb..5af841b 100644 --- a/digital/atk16_regbank.dig +++ b/digital/atk16_regbank.dig @@ -82,104 +82,6 @@ - - Ground - - - rotation - - - - Bits - 16 - - - - - - Tunnel - - - rotation - - - - NetName - Q1 - - - - - - Tunnel - - - rotation - - - - NetName - Q2 - - - - - - Tunnel - - - rotation - - - - NetName - Q3 - - - - - - Tunnel - - - rotation - - - - NetName - Q4 - - - - - - Tunnel - - - rotation - - - - NetName - Q5 - - - - - - Tunnel - - - rotation - - - - NetName - Q6 - - - - In @@ -208,104 +110,6 @@ - - Ground - - - rotation - - - - Bits - 16 - - - - - - Tunnel - - - rotation - - - - NetName - Q1 - - - - - - Tunnel - - - rotation - - - - NetName - Q2 - - - - - - Tunnel - - - rotation - - - - NetName - Q3 - - - - - - Tunnel - - - rotation - - - - NetName - Q4 - - - - - - Tunnel - - - rotation - - - - NetName - Q5 - - - - - - Tunnel - - - rotation - - - - NetName - Q6 - - - - In @@ -488,7 +292,7 @@ rotation - + NetName @@ -502,7 +306,7 @@ rotation - + NetName @@ -531,7 +335,7 @@ rotation - + NetName @@ -577,7 +381,7 @@ rotation - + NetName @@ -591,7 +395,7 @@ rotation - + NetName @@ -638,7 +442,7 @@ rotation - + NetName @@ -652,7 +456,7 @@ rotation - + NetName @@ -681,7 +485,7 @@ rotation - + NetName @@ -816,7 +620,7 @@ rotation - + NetName @@ -830,7 +634,7 @@ rotation - + NetName @@ -859,7 +663,7 @@ rotation - + NetName @@ -948,66 +752,6 @@ - - Tunnel - - - NetName - RW_A - - - - - - Tunnel - - - NetName - RW_B - - - - - - Tunnel - - - NetName - RW_C - - - - - - Tunnel - - - NetName - RW_D - - - - - - Tunnel - - - NetName - RW_E - - - - - - Tunnel - - - NetName - RW_F - - - - Testcase @@ -1020,9 +764,7 @@ C 0xF 1 1 0 X X X C 0 0 0 1 X 0xF X C 0x5 1 1 1 X 0x5 X C 0 0 0 1 X 0x5 X - -# zero register read and write -C 0xA 1 0 0 X 0 X + @@ -1051,7 +793,7 @@ C 0xA 1 0 0 X 0 X rotation - + NetName @@ -1065,7 +807,7 @@ C 0xA 1 0 0 X 0 X rotation - + NetName @@ -1094,7 +836,7 @@ C 0xA 1 0 0 X 0 X rotation - + NetName @@ -1118,18 +860,79 @@ C 0xA 1 0 0 X 0 X - Tunnel + Register - rotation - + valueIsProbe + true - NetName - Q7 + Label + RH + + + Bits + 16 - + + + + Tunnel + + + rotation + + + + NetName + Din + + + + + + Tunnel + + + rotation + + + + NetName + CLK + + + + + + Tunnel + + + NetName + Q8 + + + + + + And + + + + + Tunnel + + + rotation + + + + NetName + RW_IE + + + Tunnel @@ -1140,10 +943,70 @@ C 0xA 1 0 0 X 0 X NetName - Q7 + RW_H - + + + + Tunnel + + + NetName + RW_A + + + + + + Tunnel + + + NetName + RW_B + + + + + + Tunnel + + + NetName + RW_C + + + + + + Tunnel + + + NetName + RW_D + + + + + + Tunnel + + + NetName + RW_E + + + + + + Tunnel + + + NetName + RW_F + + + Tunnel @@ -1153,30 +1016,268 @@ C 0xA 1 0 0 X 0 X RW_G + + + + Tunnel + + + NetName + RW_H + + + + Tunnel + + + rotation + + + + NetName + Q1 + + + + + + Tunnel + + + rotation + + + + NetName + Q2 + + + + + + Tunnel + + + rotation + + + + NetName + Q3 + + + + + + Tunnel + + + rotation + + + + NetName + Q4 + + + + + + Tunnel + + + rotation + + + + NetName + Q5 + + + + + + Tunnel + + + rotation + + + + NetName + Q6 + + + + + + Tunnel + + + rotation + + + + NetName + Q7 + + + + + + Tunnel + + + rotation + + + + NetName + Q8 + + + + + + Tunnel + + + rotation + + + + NetName + Q1 + + + + + + Tunnel + + + rotation + + + + NetName + Q2 + + + + + + Tunnel + + + rotation + + + + NetName + Q3 + + + + + + Tunnel + + + rotation + + + + NetName + Q4 + + + + + + Tunnel + + + rotation + + + + NetName + Q5 + + + + + + Tunnel + + + rotation + + + + NetName + Q6 + + + + + + Tunnel + + + rotation + + + + NetName + Q7 + + + + + + Tunnel + + + rotation + + + + NetName + Q8 + + + + - - - - - - + + + + + + + + + + @@ -1221,6 +1322,10 @@ C 0xA 1 0 0 X 0 X + + + + @@ -1229,14 +1334,14 @@ C 0xA 1 0 0 X 0 X - - - - + + + + @@ -1265,38 +1370,42 @@ C 0xA 1 0 0 X 0 X - - - - + + + + - - + + - - + + - - + + + + + + @@ -1317,14 +1426,14 @@ C 0xA 1 0 0 X 0 X - - - - + + + + @@ -1381,6 +1490,10 @@ C 0xA 1 0 0 X 0 X + + + + \ No newline at end of file diff --git a/src/asm_pass2.py b/src/asm_pass2.py index 77b8fa6..261ba06 100644 --- a/src/asm_pass2.py +++ b/src/asm_pass2.py @@ -7,6 +7,7 @@ from asm_pass1 import * class Result2Line: line_num: int parts: list[str] + original_parts: list[str] @dataclass class Result2: @@ -20,16 +21,17 @@ def pass_2(result1: Result1) -> Result2: for line in result1.lines: keyword, *args = line.parts - if not keyword.startswith("@"): + if keyword in result1.operations: fn = result1.operations[keyword] output: list[list[str]] = fn(*args) else: output = [line.parts] - for parts in output: + for (idx, parts) in enumerate(output): result_lines.append(Result2Line( line_num=line.line_num, - parts=parts + parts=parts, + original_parts=line.parts if idx == 0 else ["..."] )) return Result2( diff --git a/src/asm_pass3.py b/src/asm_pass3.py index 5365e3b..e8e44d3 100644 --- a/src/asm_pass3.py +++ b/src/asm_pass3.py @@ -8,6 +8,7 @@ class Result3Line: line_num: int address: int parts: list[str] + original_parts: list[str] @dataclass class Result3: @@ -35,6 +36,7 @@ def pass_3(result2: Result2) -> Result3: line_num=line.line_num, parts=line.parts, address=address, + original_parts=line.original_parts, )) address += 1 diff --git a/src/asm_pass4.py b/src/asm_pass4.py index 96d9e65..926b354 100644 --- a/src/asm_pass4.py +++ b/src/asm_pass4.py @@ -9,6 +9,7 @@ class Result4Line: address: int word: int text: str + original_text: str @dataclass class Result4: @@ -35,6 +36,7 @@ def pass_4(result3: Result3) -> Result4: args = list(map(lambda a: translate_opt(a, result3.options), args)) text = " ".join([keyword, *args]) + original_text = " ".join(line.original_parts) if keyword in operations: fn = operations[keyword] @@ -44,6 +46,7 @@ def pass_4(result3: Result3) -> Result4: address=line.address, word=word, text=text, + original_text=original_text, )) else: try: @@ -52,10 +55,13 @@ def pass_4(result3: Result3) -> Result4: address=line.address, word=eval_expr(result3.labels, keyword), text=text, + original_text=original_text, )) except: raise Exception(f"Invalid assembly at {line.line_num + 1}\n\n{line}") + address += 1 + return Result4( operations=result3.operations, labels=result3.labels, diff --git a/src/assembler.py b/src/assembler.py index fc7bc45..4e82deb 100755 --- a/src/assembler.py +++ b/src/assembler.py @@ -67,7 +67,10 @@ for line in result4.lines: if len(result) < 2 * line.address + 1: result.extend((2 * line.address + 1 - len(result)) * nop) - print(f"{line.address:>08x} 0x{line.word:>04x} {line.text}") + out_line = f"{line.address:>08x} 0x{line.word:>04x} {line.text}" + out_spaces_n = (42 - len(out_line)) + out_spaces = out_spaces_n * " " if out_spaces_n > 0 else 4 * " " + print(f"{out_line}{out_spaces}{line.original_text}") result[2 * line.address + 0] = ((line.word >> 8) & 0xff) result[2 * line.address + 1] = ((line.word >> 0) & 0xff) diff --git a/src/assembler_eval.py b/src/assembler_eval.py index 7cfe336..691e4eb 100644 --- a/src/assembler_eval.py +++ b/src/assembler_eval.py @@ -1,13 +1,13 @@ constants: dict[str, str] = { # Registers - "rz": "0", - "ra": "1", - "rb": "2", - "rc": "3", - "rd": "4", - "re": "5", - "rf": "6", - "rg": "7", + "ra": "0", + "rb": "1", + "rc": "2", + "rd": "3", + "re": "4", + "rf": "5", + "rg": "6", + "rh": "7", # ALU instructions "al_plus": "0", "al_minus": "1", @@ -18,10 +18,10 @@ constants: dict[str, str] = { "al_sar": "6", "al_sll": "7", # ALU flags - "f_carry": "0", - "f_overflow": "1", - "f_zero": "2", - "f_sign": "3", + "carry": "0", + "overflow": "1", + "zero": "2", + "sign": "3", } Labels = dict[str, int] diff --git a/src/assembler_ops.py b/src/assembler_ops.py index e4eeac4..b55927b 100644 --- a/src/assembler_ops.py +++ b/src/assembler_ops.py @@ -4,8 +4,8 @@ from dataclasses import dataclass @dataclass class Options: - stack_pointer = "rg" - csr_scratch = "rf" + stack_pointer = "rf" + csr_scratch = "rh" @dataclass class Meta: @@ -37,7 +37,7 @@ def make_ali(meta: Meta, labels: Labels, alu_op: str, left: str, imm: str, targe alu_op_e return word -def make_ldr(meta: Meta, labels: Labels, to_reg: str, addr_reg: str) -> int: +def make_ldr(meta: Meta, labels: Labels, addr_reg: str, to_reg: str) -> int: """LDR 0010 TTTR RRXX XXXX""" to_reg_e = eval_expr(labels, to_reg, bits=3) addr_reg_e = eval_expr(labels, addr_reg, bits=3) @@ -47,15 +47,15 @@ def make_ldr(meta: Meta, labels: Labels, to_reg: str, addr_reg: str) -> int: return word def make_str(meta: Meta, labels: Labels, from_reg: str, addr_reg: str) -> int: - """STR 0011 TTTR RRXX XXXX""" + """STR 0011 XXXL LLRR RXXX""" from_reg_e = eval_expr(labels, from_reg, bits=3) addr_reg_e = eval_expr(labels, addr_reg, bits=3) word = (0b0011 << 12) + \ - (from_reg_e << 9) + \ - (addr_reg_e << 6) + (addr_reg_e << 6) + \ + (from_reg_e << 3) return word -def make_ldi(meta: Meta, labels: Labels, to_reg: str, imm: str) -> int: +def make_ldi(meta: Meta, labels: Labels, imm: str, to_reg: str) -> int: """LDI 0100 TTTI IIII IIII""" to_reg_e = eval_expr(labels, to_reg, bits=3) imm_e = eval_expr(labels, imm, bits=9) @@ -75,6 +75,7 @@ def make_jpi(meta: Meta, labels: Labels, imm: str) -> int: """JPI 0110 XXXI IIII IIII""" imm_e = eval_expr(labels, imm, bits=9) imm_e = imm_e - meta.address - 1 + imm_e = imm_e & (0b111111111) word = (0b0110 << 12) + \ imm_e return word @@ -93,6 +94,7 @@ def make_bri(meta: Meta, labels: Labels, flag_s: str, imm: str) -> int: flag_s_e = eval_expr(labels, flag_s, bits=2) imm_e = eval_expr(labels, imm, bits=9) imm_e = imm_e - meta.address - 1 + imm_e = imm_e & (0b111111111) word = (0b1000 << 12) + \ (flag_s_e << 9) + \ imm_e diff --git a/src/ext_std.py b/src/ext_std.py index a6b175a..5f41f60 100644 --- a/src/ext_std.py +++ b/src/ext_std.py @@ -52,16 +52,25 @@ def expand_spu(reg: str) -> ExpandResult: return [["str", reg, "__STACK_POINTER"]] + expand_inc("__STACK_POINTER") def expand_spo(reg: str): - return expand_dec("__STACK_POINTER") + [["ldr", reg, "__STACK_POINTER"]] + return expand_dec("__STACK_POINTER") + [["ldr", "__STACK_POINTER", reg]] def expand_csr(addr_reg: str): - return [["lpc", "__STACK_POINTER"]] + expand_spu("__STACK_POINTER") + [["jpr", addr_reg]] + return [ + ["lpc", "__CSR_SCRATCH"], + *expand_addi("__CSR_SCRATCH", "4", "__CSR_SCRATCH"), + *expand_spu("__CSR_SCRATCH"), + ["jpr", addr_reg] + ] def expand_csi(addr_imm: str): - return [["lpc", "__STACK_POINTER"]] + expand_spu("__STACK_POINTER") + [["jpr", addr_imm]] - + return [ + ["lpc", "__CSR_SCRATCH"], + *expand_addi("__CSR_SCRATCH", "4", "__CSR_SCRATCH"), + *expand_spu("__CSR_SCRATCH"), + ["jpi", addr_imm] + ] def expand_rsr(): - return expand_spo("__STACK_POINTER") + [["jpr", "__CSR_SCRATCH"]] + return expand_spo("__CSR_SCRATCH") + [["jpr", "__CSR_SCRATCH"]] expansions: OpExpansionDict = { "add": expand_add, diff --git a/src/test.atk16 b/src/test.atk16 index 8e48892..3f2d378 100644 --- a/src/test.atk16 +++ b/src/test.atk16 @@ -22,7 +22,7 @@ mov RC RA ; RA := result of sum ldi RB 30 ; RB := 30 sub RA RB RC ; RC := RA - RB - bri f_zero @success ; if result is zero, jump to success + bri zero @success ; if result is zero, jump to success ldi RA 2 ; RA := 2 to signal failure hlt diff --git a/src/test_fibo.atk16 b/src/test_fibo.atk16 index a03f14b..8bb7a6e 100644 --- a/src/test_fibo.atk16 +++ b/src/test_fibo.atk16 @@ -1,46 +1,66 @@ -@opt stack_pointer RG -@opt csr_scratch RF - +@opt stack_pointer RF +@opt csr_scratch RH @use ext_std:* +; jump over data segment + jpi program + +; data segment +@label ram_offset + 0x8000 + @label program - ; call fibo subroutine with parameter 10 - ldi RA 10 +; set up stack pointer to point to beginning of RAM + ldi ram_offset RA + ldr RA RF + +; call fibo subroutine with parameter 10 + ldi 10 RA csi fibo hlt @label fibo - ; function fibo - ; parameters: - ; RA n : u16 - ; return value: - ; RA fibo(n) : u16 +; function fibo +; parameters: +; RA n : u16 +; return value: +; RA fibo(n) : u16 - spu RB ; prelude +; store RB, RC on stack + spu RB spu RC - - subi RA 2 RA ; if n < 2, return n - bri f_sign fibo_early - - spu RD ; prelude - - ldi RB 0 ; a = 0 - ldi RC 1 ; b = 1 +; if n < 2, return n + subi RA 2 RA + bri sign fibo_early +; store also RD on stack + spu RD +; a = 0 + ldi 0 RB +; b = 1 + ldi 1 RC @label fibo_loop - add RB RC RD ; v = a + b - mov RC RB ; a = b - mov RD RC ; b = v - dec RA ; n -= 1 - bri f_zero fibo_done ; loop while n > 0 +; v = a + b + add RB RC RD +; a = b + mov RC RB +; b = v + mov RD RC +; n -= 1 + dec RA +; loop while n > 0 + bri zero fibo_done jpi fibo_loop - @label fibo_early +; restore used registers spo RC spo RB +; return from subroutine rsr @label fibo_done mov RD RA - spo RD ; restore registers +; restore used registers + spo RD spo RC spo RB +; return from subroutine rsr diff --git a/src/ucode.py b/src/ucode.py index 9745a7e..1d050c8 100755 --- a/src/ucode.py +++ b/src/ucode.py @@ -20,9 +20,9 @@ MEM_IE = 0b0000_0000_0001_0000 MEM_OE = 0b0000_0000_0010_0000 RW_IE = 0b0000_0000_0100_0000 R1_OE = 0b0000_0000_1000_0000 -IM_M = 0b0000_0001_0000_0000 +R2_OE = 0b0000_0001_0000_0000 IR_IE = 0b0000_0010_0000_0000 -unused = 0b0000_0100_0000_0000 +IM_M = 0b0000_0100_0000_0000 LI_OE = 0b0000_1000_0000_0000 ALU_OE = 0b0001_0000_0000_0000 FR_IE = 0b0010_0000_0000_0000 @@ -51,8 +51,8 @@ ucode = [ not_branch([*fetch, IM_M|ALU_OE|FR_IE|RW_IE, US_RS, 0, 0, 0, 0]), # LDR 0010 TTTR RRXX XXXX not_branch([*fetch, R1_OE|MAR_IE, MEM_OE|RW_IE, US_RS, 0, 0, 0]), - # STR 0011 TTTR RRXX XXXX - not_branch([*fetch, R1_OE|MAR_IE, R1_OE|MEM_IE, US_RS, 0, 0, 0]), + # STR 0011 XXXL LLRR RXXX + not_branch([*fetch, R1_OE|MAR_IE, R2_OE|MEM_IE, US_RS, 0, 0, 0]), # LDI 0100 TTTI IIII IIII not_branch([*fetch, LI_OE|RW_IE, US_RS, 0, 0, 0, 0]), # JPR 0101 XXXR RRXX XXXX -- cgit v1.3