From f1096f78f89e10b867b6ff7689d0a8777855b451 Mon Sep 17 00:00:00 2001 From: Jan Tuomi Date: Sun, 29 Dec 2024 21:05:56 +0200 Subject: Rename mem_fsm -> bram_fsm --- atk16_fpga/bram_fsm.v | 58 +++++++++++++ atk16_fpga/bram_fsm_tb.gtkw | 32 ++++++++ atk16_fpga/bram_fsm_tb.v | 84 +++++++++++++++++++ atk16_fpga/cu.v | 2 +- atk16_fpga/cu_tb.v | 194 ++++++++++++++++++++++---------------------- atk16_fpga/mem_fsm.v | 58 ------------- atk16_fpga/mem_fsm_tb.gtkw | 32 -------- atk16_fpga/mem_fsm_tb.v | 84 ------------------- 8 files changed, 272 insertions(+), 272 deletions(-) create mode 100644 atk16_fpga/bram_fsm.v create mode 100644 atk16_fpga/bram_fsm_tb.gtkw create mode 100644 atk16_fpga/bram_fsm_tb.v delete mode 100644 atk16_fpga/mem_fsm.v delete mode 100644 atk16_fpga/mem_fsm_tb.gtkw delete mode 100644 atk16_fpga/mem_fsm_tb.v diff --git a/atk16_fpga/bram_fsm.v b/atk16_fpga/bram_fsm.v new file mode 100644 index 0000000..763b853 --- /dev/null +++ b/atk16_fpga/bram_fsm.v @@ -0,0 +1,58 @@ +`default_nettype none + +`define ST_IDLE 3'd0 +`define ST_READ 3'd1 +`define ST_WRITE 3'd2 + +module bram_fsm( + input clk, + input [15:0] addr, + input [15:0] data_in, + input read_en, + input write_en, + + output wire [15:0] data_out, + output reg done +); + reg wr, rd; + reg [15:0] bram_addr; + reg [2:0] state = 0; + bram bram_inst( + .clk(clk), + .addr(bram_addr), + .cs_n(1'd0), + .wr_n(~wr), + .rd_n(~rd), + .bram_data_in(data_in), + .bram_data_out(data_out) + ); + + always @(posedge clk) begin + case (state) + `ST_IDLE: begin + done <= 0; + if (~done && read_en) begin + state <= `ST_READ; + bram_addr <= addr; + rd <= 1; + wr <= 0; + end + else if (~done && write_en) begin + state <= `ST_WRITE; + bram_addr <= addr; + rd <= 0; + wr <= 1; + end + end + `ST_READ: begin + state <= `ST_IDLE; + done <= 1; + end + `ST_WRITE: begin + state <= `ST_IDLE; + done <= 1; + end + endcase + end + +endmodule diff --git a/atk16_fpga/bram_fsm_tb.gtkw b/atk16_fpga/bram_fsm_tb.gtkw new file mode 100644 index 0000000..0f8b544 --- /dev/null +++ b/atk16_fpga/bram_fsm_tb.gtkw @@ -0,0 +1,32 @@ +[*] +[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI +[*] Thu Dec 26 11:58:12 2024 +[*] +[dumpfile] "/Users/jantuomi/Projects/Personal/ATK16/atk16_fpga/bram_fsm_tb.vcd" +[dumpfile_mtime] "Thu Dec 26 11:57:15 2024" +[dumpfile_size] 1302 +[savefile] "/Users/jantuomi/Projects/Personal/ATK16/atk16_fpga/bram_fsm_tb.gtkw" +[timestart] 0 +[size] 1280 600 +[pos] -1 -1 +*-16.373917 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +[treeopen] bram_fsm_tb. +[treeopen] bram_fsm_tb.dut. +[sst_width] 240 +[signals_width] 144 +[sst_expanded] 1 +[sst_vpaned_height] 159 +@28 +bram_fsm_tb.clk +bram_fsm_tb.start_read +bram_fsm_tb.start_write +@22 +bram_fsm_tb.addr[15:0] +bram_fsm_tb.data_in[15:0] +bram_fsm_tb.data_out[15:0] +@28 +bram_fsm_tb.done +@29 +bram_fsm_tb.dut.state[2:0] +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/atk16_fpga/bram_fsm_tb.v b/atk16_fpga/bram_fsm_tb.v new file mode 100644 index 0000000..1ec5a88 --- /dev/null +++ b/atk16_fpga/bram_fsm_tb.v @@ -0,0 +1,84 @@ +`default_nettype none +`define DUMPSTR(x) `"x.vcd`" +`timescale 10 ns / 100 ps + +module bram_fsm_tb(); + + reg clk, rst, read_en, write_en; + reg [15:0] addr, data_in; + wire done; + wire [15:0] data_out; + + bram_fsm dut( + .clk(clk), + .addr(addr), + .data_in(data_in), + .read_en(read_en), + .write_en(write_en), + .data_out(data_out), + .done(done) + ); + + // Clock generation + always #5 clk = ~clk; // 100 MHz clock + + reg failed; + initial begin + failed = 0; + $dumpfile(`DUMPSTR(`VCD_OUTPUT)); + $dumpvars(0, bram_fsm_tb); + + clk = 0; + rst = 0; + read_en = 0; + write_en = 0; + #10 + + // test read + dut.bram_inst.mem[0] = 16'hffff; + addr = 16'd0; + read_en = 1; + write_en = 0; + + while (!done) #10; + + if (data_out == 16'hffff && done == 1) begin + $display("\033[0;32m[PASS]\033[0m Read: data is available and done is 1 as expected"); + end else begin + $display("\033[0;31m[FAIL]\033[0m Read: done is %d (expected 1), data is %04h (expected ffff)", done, data_out); + failed = 1; + end + + read_en = 0; + write_en = 0; + #10 + + // test write + addr = 16'd1; + data_in = 16'hffff; + read_en = 0; + write_en = 1; + + while (!done) #10; + + if (dut.bram_inst.mem[1] == 16'hffff && done == 1) begin + $display("\033[0;32m[PASS]\033[0m Write: data is available and done is 1 as expected"); + end else begin + $display("\033[0;31m[FAIL]\033[0m Write: done is %d (expected 0), data is %04h (expected FFFF)", done, data_out); + failed = 1; + end + + read_en = 0; + write_en = 0; + + #5 + if (failed) begin + $display("🛑 \033[0;31mTest suite failed\033[0m"); + $fatal(1); + end else + $display("✅ \033[0;32mTest suite passed\033[0m"); + + $finish; + end + +endmodule diff --git a/atk16_fpga/cu.v b/atk16_fpga/cu.v index 13bc804..ce8998b 100644 --- a/atk16_fpga/cu.v +++ b/atk16_fpga/cu.v @@ -89,7 +89,7 @@ module cu( reg mem_read_en, mem_write_en; wire mem_done; wire [15:0] mem_data_out; - mem_fsm mem_fsm_inst( + bram_fsm bram_fsm_inst( .clk(clk), .addr(mem_addr), .data_in(mem_data_in), diff --git a/atk16_fpga/cu_tb.v b/atk16_fpga/cu_tb.v index ce4a21d..dd7f887 100644 --- a/atk16_fpga/cu_tb.v +++ b/atk16_fpga/cu_tb.v @@ -30,12 +30,12 @@ module cu_tb(); #10 // Wait for reset phase to finish // set up halt instruction at PC = 1, used by all tests - dut.mem_fsm_inst.bram_inst.mem[1] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[1] = { 4'b1111, 12'd0 }; // HLT // test ALR dut.regbank[0] = 16'd10; dut.regbank[1] = 16'd20; - dut.mem_fsm_inst.bram_inst.mem[0] = { 4'b0000, 3'd2, 3'd0, 3'd1, 3'd0 }; // ALR RC, RA, RB, S=PLUS + dut.bram_fsm_inst.bram_inst.mem[0] = { 4'b0000, 3'd2, 3'd0, 3'd1, 3'd0 }; // ALR RC, RA, RB, S=PLUS expected = 16'd30; #200 if (dut.regbank[2] == expected) begin @@ -48,7 +48,7 @@ module cu_tb(); // test ALI dut.regbank[0] = 16'd10; - dut.mem_fsm_inst.bram_inst.mem[0] = { 4'b0001, 3'd2, 3'd0, 3'd7, 3'd0 }; // ALI RC, RA, 7, S=PLUS + dut.bram_fsm_inst.bram_inst.mem[0] = { 4'b0001, 3'd2, 3'd0, 3'd7, 3'd0 }; // ALI RC, RA, 7, S=PLUS expected = 16'd17; #200 if (dut.regbank[2] == expected) begin @@ -60,9 +60,9 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test LDR, absolute addressing - dut.mem_fsm_inst.bram_inst.mem[16'd100] = 16'hffff; + dut.bram_fsm_inst.bram_inst.mem[16'd100] = 16'hffff; dut.regbank[1] = 16'd100; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // LDR RA, RB, absolute, direct + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // LDR RA, RB, absolute, direct expected = 16'hffff; #200 if (dut.regbank[0] == expected) begin @@ -74,9 +74,9 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test LDR, relative addressing - dut.mem_fsm_inst.bram_inst.mem[16'd10] = 16'hffff; + dut.bram_fsm_inst.bram_inst.mem[16'd10] = 16'hffff; dut.regbank[1] = 16'd10; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // LDR RA, RB, relative, direct + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // LDR RA, RB, relative, direct expected = 16'hffff; #200 if (dut.regbank[0] == expected) begin @@ -88,10 +88,10 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test LDR, absolute addressing, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd100] = 16'd200; - dut.mem_fsm_inst.bram_inst.mem[16'd200] = 16'hffff; + dut.bram_fsm_inst.bram_inst.mem[16'd100] = 16'd200; + dut.bram_fsm_inst.bram_inst.mem[16'd200] = 16'hffff; dut.regbank[1] = 16'd100; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // LDR RA, RB, absolute, indirect + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // LDR RA, RB, absolute, indirect expected = 16'hffff; #200 if (dut.regbank[0] == expected) begin @@ -103,10 +103,10 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test LDR, relative addressing, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd10] = 16'd20; - dut.mem_fsm_inst.bram_inst.mem[16'd20] = 16'hffff; + dut.bram_fsm_inst.bram_inst.mem[16'd10] = 16'd20; + dut.bram_fsm_inst.bram_inst.mem[16'd20] = 16'hffff; dut.regbank[1] = 16'd10; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // LDR RA, RB, relative, indirect + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // LDR RA, RB, relative, indirect expected = 16'hffff; #200 if (dut.regbank[0] == expected) begin @@ -120,13 +120,13 @@ module cu_tb(); // test STR, absolute addressing, direct dut.regbank[0] = 16'hfafa; dut.regbank[1] = 16'd100; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // STR RB, RA, absolute, direct + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // STR RB, RA, absolute, direct expected = 16'hfafa; - #200 if (dut.mem_fsm_inst.bram_inst.mem[16'd100] == expected) begin + #200 if (dut.bram_fsm_inst.bram_inst.mem[16'd100] == expected) begin $display("\033[0;32m[PASS]\033[0m STR direct absolute ok"); end else begin - $display("\033[0;31m[FAIL]\033[0m STR direct absolute not working, memory location contains %04h, expected %04h", dut.mem_fsm_inst.bram_inst.mem[16'd100], expected); + $display("\033[0;31m[FAIL]\033[0m STR direct absolute not working, memory location contains %04h, expected %04h", dut.bram_fsm_inst.bram_inst.mem[16'd100], expected); failed = 1; end rst = 1; #10 rst = 0; #10 @@ -134,13 +134,13 @@ module cu_tb(); // test STR, relative addressing, direct dut.regbank[0] = 16'hafaf; dut.regbank[1] = 16'd10; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // STR RB, RA, relative, direct + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // STR RB, RA, relative, direct expected = 16'hafaf; - #200 if (dut.mem_fsm_inst.bram_inst.mem[16'd10] == expected) begin + #200 if (dut.bram_fsm_inst.bram_inst.mem[16'd10] == expected) begin $display("\033[0;32m[PASS]\033[0m STR direct relative ok"); end else begin - $display("\033[0;31m[FAIL]\033[0m STR direct relative not working, memory location contains %04h, expected %04h", dut.mem_fsm_inst.bram_inst.mem[16'd10], expected); + $display("\033[0;31m[FAIL]\033[0m STR direct relative not working, memory location contains %04h, expected %04h", dut.bram_fsm_inst.bram_inst.mem[16'd10], expected); failed = 1; end rst = 1; #10 rst = 0; #10 @@ -148,14 +148,14 @@ module cu_tb(); // test STR, absolute addressing, indirect dut.regbank[0] = 16'hfafa; dut.regbank[1] = 16'd100; - dut.mem_fsm_inst.bram_inst.mem[16'd100] = 16'd200; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // STR RB, RA, absolute, indirect + dut.bram_fsm_inst.bram_inst.mem[16'd100] = 16'd200; + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // STR RB, RA, absolute, indirect expected = 16'hfafa; - #200 if (dut.mem_fsm_inst.bram_inst.mem[16'd200] == expected) begin + #200 if (dut.bram_fsm_inst.bram_inst.mem[16'd200] == expected) begin $display("\033[0;32m[PASS]\033[0m STR indirect absolute ok"); end else begin - $display("\033[0;31m[FAIL]\033[0m STR indirect absolute not working, memory location contains %04h, expected %04h", dut.mem_fsm_inst.bram_inst.mem[16'd200], expected); + $display("\033[0;31m[FAIL]\033[0m STR indirect absolute not working, memory location contains %04h, expected %04h", dut.bram_fsm_inst.bram_inst.mem[16'd200], expected); failed = 1; end rst = 1; #10 rst = 0; #10 @@ -163,21 +163,21 @@ module cu_tb(); // test STR, relative addressing, indirect dut.regbank[0] = 16'hafaf; dut.regbank[1] = -16'd10; - dut.mem_fsm_inst.bram_inst.mem[16'd10] = 16'd20; - dut.mem_fsm_inst.bram_inst.mem[16'd20] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // STR RB, RA, relative, indirect + dut.bram_fsm_inst.bram_inst.mem[16'd10] = 16'd20; + dut.bram_fsm_inst.bram_inst.mem[16'd20] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // STR RB, RA, relative, indirect dut.pc = 16'd20; expected = 16'hafaf; - #200 if (dut.mem_fsm_inst.bram_inst.mem[16'd20] == expected) begin + #200 if (dut.bram_fsm_inst.bram_inst.mem[16'd20] == expected) begin $display("\033[0;32m[PASS]\033[0m STR indirect relative ok"); end else begin - $display("\033[0;31m[FAIL]\033[0m STR indirect relative not working, memory location contains %04h, expected %04h", dut.mem_fsm_inst.bram_inst.mem[16'd20], expected); + $display("\033[0;31m[FAIL]\033[0m STR indirect relative not working, memory location contains %04h, expected %04h", dut.bram_fsm_inst.bram_inst.mem[16'd20], expected); failed = 1; end rst = 1; #10 rst = 0; #10 // test LDI, absolute addressing, direct - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd123, 1'd1, 1'd1 }; // LDI RA, 1, absolute, direct + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd123, 1'd1, 1'd1 }; // LDI RA, 1, absolute, direct expected = 16'd123; #200 if (dut.regbank[0] == expected) begin @@ -189,7 +189,7 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test LDI, relative addressing, direct - dut.mem_fsm_inst.bram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd1 }; // LDI RA, 1, relative, direct + dut.bram_fsm_inst.bram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd1 }; // LDI RA, 1, relative, direct dut.pc = 16'd150; expected = 16'd130; @@ -202,8 +202,8 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test LDI, absolute addressing, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd50, 1'd1, 1'd0 }; // LDI RA, 1, absolute, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd50] = 16'd123; + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd50, 1'd1, 1'd0 }; // LDI RA, 1, absolute, indirect + dut.bram_fsm_inst.bram_inst.mem[16'd50] = 16'd123; expected = 16'd123; #200 if (dut.regbank[0] == expected) begin @@ -215,8 +215,8 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test LDI, relative addressing, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd0 }; // LDI RA, 1, relative, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd130] = 16'd123; + dut.bram_fsm_inst.bram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd0 }; // LDI RA, 1, relative, indirect + dut.bram_fsm_inst.bram_inst.mem[16'd130] = 16'd123; dut.pc = 16'd150; expected = 16'd123; @@ -230,8 +230,8 @@ module cu_tb(); // test JPR, absolute addressing, direct dut.regbank[0] = 16'd100; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd1, 3'd0, 7'd0 }; // JPR RA, absolute, direct - dut.mem_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd1, 3'd0, 7'd0 }; // JPR RA, absolute, direct + dut.bram_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT expected = 16'd101; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -244,8 +244,8 @@ module cu_tb(); // test JPR, relative addressing, direct dut.regbank[0] = 16'd50; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0101, 1'd0, 1'd1, 3'd0, 7'd0 }; // JPR RA, relative, direct - dut.mem_fsm_inst.bram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0101, 1'd0, 1'd1, 3'd0, 7'd0 }; // JPR RA, relative, direct + dut.bram_fsm_inst.bram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT expected = 16'd51; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -258,9 +258,9 @@ module cu_tb(); // test JPR, absolute addressing, indirect dut.regbank[0] = 16'd100; - dut.mem_fsm_inst.bram_inst.mem[16'd100] = 16'd200; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd0, 3'd0, 7'd0 }; // JPR RA, absolute, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd100] = 16'd200; + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd0, 3'd0, 7'd0 }; // JPR RA, absolute, indirect + dut.bram_fsm_inst.bram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT expected = 16'd201; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -273,9 +273,9 @@ module cu_tb(); // test JPR, relative addressing, indirect dut.regbank[0] = 16'd50; - dut.mem_fsm_inst.bram_inst.mem[16'd60] = 16'd100; - dut.mem_fsm_inst.bram_inst.mem[16'd10] = { 4'b0101, 1'd0, 1'd0, 3'd0, 7'd0 }; // JPR RA, relative, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd60] = 16'd100; + dut.bram_fsm_inst.bram_inst.mem[16'd10] = { 4'b0101, 1'd0, 1'd0, 3'd0, 7'd0 }; // JPR RA, relative, indirect + dut.bram_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT dut.pc = 16'd10; expected = 16'd101; // PC ends up at &HLT + 1 @@ -288,8 +288,8 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test JPI, absolute addressing, direct - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0110, 1'd1, 1'd1, 10'd123 }; // JPI 123, absolute, direct - dut.mem_fsm_inst.bram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0110, 1'd1, 1'd1, 10'd123 }; // JPI 123, absolute, direct + dut.bram_fsm_inst.bram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT expected = 16'd124; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -301,8 +301,8 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test JPI, relative addressing, direct - dut.mem_fsm_inst.bram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd1, -10'd20 }; // JPI -20, relative, direct - dut.mem_fsm_inst.bram_inst.mem[16'd10] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd1, -10'd20 }; // JPI -20, relative, direct + dut.bram_fsm_inst.bram_inst.mem[16'd10] = { 4'b1111, 12'd0 }; // HLT dut.pc = 16'd30; expected = 16'd11; // PC ends up at &HLT + 1 @@ -315,9 +315,9 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test JPI, absolute addressing, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd10] = { 4'b0110, 1'd1, 1'd0, 10'd50 }; // JPI 50, absolute, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd50] = 16'd123; - dut.mem_fsm_inst.bram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd10] = { 4'b0110, 1'd1, 1'd0, 10'd50 }; // JPI 50, absolute, indirect + dut.bram_fsm_inst.bram_inst.mem[16'd50] = 16'd123; + dut.bram_fsm_inst.bram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT dut.pc = 16'd10; expected = 16'd124; // PC ends up at &HLT + 1 @@ -330,9 +330,9 @@ module cu_tb(); rst = 1; #10 rst = 0; #10 // test JPI, relative addressing, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd0, -10'd20 }; // JPI -20, relative, indirect - dut.mem_fsm_inst.bram_inst.mem[16'd10] = 16'd50; - dut.mem_fsm_inst.bram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd0, -10'd20 }; // JPI -20, relative, indirect + dut.bram_fsm_inst.bram_inst.mem[16'd10] = 16'd50; + dut.bram_fsm_inst.bram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT dut.pc = 16'd30; expected = 16'd51; // PC ends up at &HLT + 1 @@ -347,10 +347,10 @@ module cu_tb(); // test BRR, absolute addressing, direct, true branch dut.regbank[0] = 16'd100; dut.regbank[2] = 16'd110; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS - dut.mem_fsm_inst.bram_inst.mem[16'd1] = { 4'b0111, 1'd1, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=ZERO - dut.mem_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT - dut.mem_fsm_inst.bram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS + dut.bram_fsm_inst.bram_inst.mem[16'd1] = { 4'b0111, 1'd1, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=ZERO + dut.bram_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT expected = 16'd111; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -364,10 +364,10 @@ module cu_tb(); // test BRR, absolute addressing, direct, false branch dut.regbank[0] = 16'd100; dut.regbank[2] = 16'd110; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS - dut.mem_fsm_inst.bram_inst.mem[16'd1] = { 4'b0111, 1'd1, 1'd1, 2'd1, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=NEGATIVE - dut.mem_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT - dut.mem_fsm_inst.bram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS + dut.bram_fsm_inst.bram_inst.mem[16'd1] = { 4'b0111, 1'd1, 1'd1, 2'd1, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=NEGATIVE + dut.bram_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT expected = 16'd3; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -382,10 +382,10 @@ module cu_tb(); dut.regbank[0] = 16'd100; dut.regbank[2] = 16'd109; dut.pc = 16'd10; - dut.mem_fsm_inst.bram_inst.mem[16'd10] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS - dut.mem_fsm_inst.bram_inst.mem[16'd11] = { 4'b0111, 1'd0, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, direct, F=ZERO - dut.mem_fsm_inst.bram_inst.mem[16'd12] = { 4'b1111, 12'd0 }; // HLT - dut.mem_fsm_inst.bram_inst.mem[16'd120] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd10] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS + dut.bram_fsm_inst.bram_inst.mem[16'd11] = { 4'b0111, 1'd0, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, direct, F=ZERO + dut.bram_fsm_inst.bram_inst.mem[16'd12] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd120] = { 4'b1111, 12'd0 }; // HLT expected = 16'd121; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -399,11 +399,11 @@ module cu_tb(); // test BRR, absolute addressing, indirect dut.regbank[0] = 16'd100; dut.regbank[2] = 16'd110; - dut.mem_fsm_inst.bram_inst.mem[16'd110] = 16'd200; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS - dut.mem_fsm_inst.bram_inst.mem[16'd1] = { 4'b0111, 1'd1, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, indirect, F=ZERO - dut.mem_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT - dut.mem_fsm_inst.bram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd110] = 16'd200; + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS + dut.bram_fsm_inst.bram_inst.mem[16'd1] = { 4'b0111, 1'd1, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, indirect, F=ZERO + dut.bram_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT expected = 16'd201; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -418,11 +418,11 @@ module cu_tb(); dut.regbank[0] = 16'd100; dut.regbank[2] = 16'd109; dut.pc = 16'd10; - dut.mem_fsm_inst.bram_inst.mem[16'd10] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS - dut.mem_fsm_inst.bram_inst.mem[16'd11] = { 4'b0111, 1'd0, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, indirect, F=ZERO - dut.mem_fsm_inst.bram_inst.mem[16'd12] = { 4'b1111, 12'd0 }; // HLT - dut.mem_fsm_inst.bram_inst.mem[16'd120] = 16'd130; - dut.mem_fsm_inst.bram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd10] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS + dut.bram_fsm_inst.bram_inst.mem[16'd11] = { 4'b0111, 1'd0, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, indirect, F=ZERO + dut.bram_fsm_inst.bram_inst.mem[16'd12] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd120] = 16'd130; + dut.bram_fsm_inst.bram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT expected = 16'd131; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -435,10 +435,10 @@ module cu_tb(); // test BRI, absolute addressing, direct, true branch dut.regbank[0] = 16'd100; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS - dut.mem_fsm_inst.bram_inst.mem[16'd1] = { 4'b1000, 1'd1, 1'd1, 2'd0, 8'd100 }; // BRI 100, absolute, direct, F=ZERO - dut.mem_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT - dut.mem_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS + dut.bram_fsm_inst.bram_inst.mem[16'd1] = { 4'b1000, 1'd1, 1'd1, 2'd0, 8'd100 }; // BRI 100, absolute, direct, F=ZERO + dut.bram_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT expected = 16'd101; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -451,10 +451,10 @@ module cu_tb(); // test BRI, absolute addressing, direct, false branch dut.regbank[0] = 16'd100; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS - dut.mem_fsm_inst.bram_inst.mem[16'd1] = { 4'b1000, 1'd1, 1'd1, 2'd1, 8'd100 }; // BRI 100, absolute, direct, F=NEGATIVE - dut.mem_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT - dut.mem_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS + dut.bram_fsm_inst.bram_inst.mem[16'd1] = { 4'b1000, 1'd1, 1'd1, 2'd1, 8'd100 }; // BRI 100, absolute, direct, F=NEGATIVE + dut.bram_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT expected = 16'd3; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -468,10 +468,10 @@ module cu_tb(); // test BRI, relative addressing, direct dut.regbank[0] = 16'd100; dut.pc = 16'd10; - dut.mem_fsm_inst.bram_inst.mem[16'd10] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS - dut.mem_fsm_inst.bram_inst.mem[16'd11] = { 4'b1000, 1'd0, 1'd1, 2'd0, 8'd9 }; // BRI 9, relative, direct, F=ZERO - dut.mem_fsm_inst.bram_inst.mem[16'd12] = { 4'b1111, 12'd0 }; // HLT - dut.mem_fsm_inst.bram_inst.mem[16'd20] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd10] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS + dut.bram_fsm_inst.bram_inst.mem[16'd11] = { 4'b1000, 1'd0, 1'd1, 2'd0, 8'd9 }; // BRI 9, relative, direct, F=ZERO + dut.bram_fsm_inst.bram_inst.mem[16'd12] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd20] = { 4'b1111, 12'd0 }; // HLT expected = 16'd21; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -484,11 +484,11 @@ module cu_tb(); // test BRI, absolute addressing, indirect dut.regbank[0] = 16'd100; - dut.mem_fsm_inst.bram_inst.mem[16'd100] = 16'd200; - dut.mem_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS - dut.mem_fsm_inst.bram_inst.mem[16'd1] = { 4'b1000, 1'd1, 1'd0, 2'd0, 8'd100 }; // BRI 100, absolute, indirect, F=ZERO - dut.mem_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT - dut.mem_fsm_inst.bram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd100] = 16'd200; + dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS + dut.bram_fsm_inst.bram_inst.mem[16'd1] = { 4'b1000, 1'd1, 1'd0, 2'd0, 8'd100 }; // BRI 100, absolute, indirect, F=ZERO + dut.bram_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT expected = 16'd201; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin @@ -502,11 +502,11 @@ module cu_tb(); // test BRI, relative addressing, indirect dut.regbank[0] = 16'd100; dut.pc = 16'd10; - dut.mem_fsm_inst.bram_inst.mem[16'd10] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS - dut.mem_fsm_inst.bram_inst.mem[16'd11] = { 4'b1000, 1'd0, 1'd0, 2'd0, 8'd9 }; // BRI 9, relative, indirect, F=ZERO - dut.mem_fsm_inst.bram_inst.mem[16'd12] = { 4'b1111, 12'd0 }; // HLT - dut.mem_fsm_inst.bram_inst.mem[16'd20] = 16'd130; - dut.mem_fsm_inst.bram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd10] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS + dut.bram_fsm_inst.bram_inst.mem[16'd11] = { 4'b1000, 1'd0, 1'd0, 2'd0, 8'd9 }; // BRI 9, relative, indirect, F=ZERO + dut.bram_fsm_inst.bram_inst.mem[16'd12] = { 4'b1111, 12'd0 }; // HLT + dut.bram_fsm_inst.bram_inst.mem[16'd20] = 16'd130; + dut.bram_fsm_inst.bram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT expected = 16'd131; // PC ends up at &HLT + 1 #200 if (dut.pc == expected) begin diff --git a/atk16_fpga/mem_fsm.v b/atk16_fpga/mem_fsm.v deleted file mode 100644 index 051705e..0000000 --- a/atk16_fpga/mem_fsm.v +++ /dev/null @@ -1,58 +0,0 @@ -`default_nettype none - -`define ST_IDLE 3'd0 -`define ST_READ 3'd1 -`define ST_WRITE 3'd2 - -module mem_fsm( - input clk, - input [15:0] addr, - input [15:0] data_in, - input read_en, - input write_en, - - output wire [15:0] data_out, - output reg done -); - reg wr, rd; - reg [15:0] bram_addr; - reg [2:0] state = 0; - bram bram_inst( - .clk(clk), - .addr(bram_addr), - .cs_n(1'd0), - .wr_n(~wr), - .rd_n(~rd), - .bram_data_in(data_in), - .bram_data_out(data_out) - ); - - always @(posedge clk) begin - case (state) - `ST_IDLE: begin - done <= 0; - if (~done && read_en) begin - state <= `ST_READ; - bram_addr <= addr; - rd <= 1; - wr <= 0; - end - else if (~done && write_en) begin - state <= `ST_WRITE; - bram_addr <= addr; - rd <= 0; - wr <= 1; - end - end - `ST_READ: begin - state <= `ST_IDLE; - done <= 1; - end - `ST_WRITE: begin - state <= `ST_IDLE; - done <= 1; - end - endcase - end - -endmodule diff --git a/atk16_fpga/mem_fsm_tb.gtkw b/atk16_fpga/mem_fsm_tb.gtkw deleted file mode 100644 index 6e8015a..0000000 --- a/atk16_fpga/mem_fsm_tb.gtkw +++ /dev/null @@ -1,32 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Thu Dec 26 11:58:12 2024 -[*] -[dumpfile] "/Users/jantuomi/Projects/Personal/ATK16/atk16_fpga/mem_fsm_tb.vcd" -[dumpfile_mtime] "Thu Dec 26 11:57:15 2024" -[dumpfile_size] 1302 -[savefile] "/Users/jantuomi/Projects/Personal/ATK16/atk16_fpga/mem_fsm_tb.gtkw" -[timestart] 0 -[size] 1280 600 -[pos] -1 -1 -*-16.373917 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -[treeopen] mem_fsm_tb. -[treeopen] mem_fsm_tb.dut. -[sst_width] 240 -[signals_width] 144 -[sst_expanded] 1 -[sst_vpaned_height] 159 -@28 -mem_fsm_tb.clk -mem_fsm_tb.start_read -mem_fsm_tb.start_write -@22 -mem_fsm_tb.addr[15:0] -mem_fsm_tb.data_in[15:0] -mem_fsm_tb.data_out[15:0] -@28 -mem_fsm_tb.done -@29 -mem_fsm_tb.dut.state[2:0] -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/atk16_fpga/mem_fsm_tb.v b/atk16_fpga/mem_fsm_tb.v deleted file mode 100644 index 8460327..0000000 --- a/atk16_fpga/mem_fsm_tb.v +++ /dev/null @@ -1,84 +0,0 @@ -`default_nettype none -`define DUMPSTR(x) `"x.vcd`" -`timescale 10 ns / 100 ps - -module mem_fsm_tb(); - - reg clk, rst, read_en, write_en; - reg [15:0] addr, data_in; - wire done; - wire [15:0] data_out; - - mem_fsm dut( - .clk(clk), - .addr(addr), - .data_in(data_in), - .read_en(read_en), - .write_en(write_en), - .data_out(data_out), - .done(done) - ); - - // Clock generation - always #5 clk = ~clk; // 100 MHz clock - - reg failed; - initial begin - failed = 0; - $dumpfile(`DUMPSTR(`VCD_OUTPUT)); - $dumpvars(0, mem_fsm_tb); - - clk = 0; - rst = 0; - read_en = 0; - write_en = 0; - #10 - - // test read - dut.bram_inst.mem[0] = 16'hffff; - addr = 16'd0; - read_en = 1; - write_en = 0; - - while (!done) #10; - - if (data_out == 16'hffff && done == 1) begin - $display("\033[0;32m[PASS]\033[0m Read: data is available and done is 1 as expected"); - end else begin - $display("\033[0;31m[FAIL]\033[0m Read: done is %d (expected 1), data is %04h (expected ffff)", done, data_out); - failed = 1; - end - - read_en = 0; - write_en = 0; - #10 - - // test write - addr = 16'd1; - data_in = 16'hffff; - read_en = 0; - write_en = 1; - - while (!done) #10; - - if (dut.bram_inst.mem[1] == 16'hffff && done == 1) begin - $display("\033[0;32m[PASS]\033[0m Write: data is available and done is 1 as expected"); - end else begin - $display("\033[0;31m[FAIL]\033[0m Write: done is %d (expected 0), data is %04h (expected FFFF)", done, data_out); - failed = 1; - end - - read_en = 0; - write_en = 0; - - #5 - if (failed) begin - $display("🛑 \033[0;31mTest suite failed\033[0m"); - $fatal(1); - end else - $display("✅ \033[0;32mTest suite passed\033[0m"); - - $finish; - end - -endmodule -- cgit v1.3