From f7dd9705d44b9cee5103b267797c0449d42319df Mon Sep 17 00:00:00 2001 From: Jan Tuomi Date: Sat, 11 Nov 2023 14:40:25 +0200 Subject: WIP functions --- asm/test_py_src.atk16 | 74 ++++++++++++++++++++++++++++----------------------- 1 file changed, 40 insertions(+), 34 deletions(-) (limited to 'asm/test_py_src.atk16') diff --git a/asm/test_py_src.atk16 b/asm/test_py_src.atk16 index c035b72..ca44267 100644 --- a/asm/test_py_src.atk16 +++ b/asm/test_py_src.atk16 @@ -31,7 +31,7 @@ @address 0x0 ldi vt_stack_addr RA - ldr RA __STACK_POINTER + ldr RA SP jpi program_segment @address vector_table @@ -75,42 +75,48 @@ -@label main -; -; - ldi 1 RA +; +@label func +; stack frame: ['arg1', 'arg2', 'a'] + addi SP 1 SP +; (arg1) + ldi ${SP - 3} RA + ldr RA RA + spu RA + spo RA + ldi ${SP - 1} RB + str RA RB +; +; +; BinOp lhs +; (a) + ldi ${SP - 1} RA + ldr RA RA spu RA +; BinOp rhs +; (a) + ldi ${SP - 1} RA + ldr RA RA + spu RA + spo RB spo RA - addi RA 0 RA - bri zero If_false_branch_0 -; - ldi 2 RA + add RA RB RA spu RA - jpi If_end_branch_1 -@label If_false_branch_0 -; + subi SP 1 SP + rsr + +@label main +; stack frame: ['b'] + addi SP 1 SP +; +; + ldi 1 RA + spu RA +; ldi 3 RA spu RA -@label If_end_branch_1 -; -@label While_test_2 -; - ldi 3 RB - spu RB + csi func spo RA - addi RA 0 RA - bri zero While_else_3 -; - ldi 4 RB - spu RB -; - jpi While_end_4 -; - ldi 5 RB - spu RB - jpi While_test_2 -@label While_else_3 -; - ldi 6 RB - spu RB -@label While_end_4 \ No newline at end of file + ldi ${SP - 1} RB + str RA RB + subi SP 1 SP -- cgit v1.3