From 6f68c0febdbfd6138fa95f77bc09785bde8a8371 Mon Sep 17 00:00:00 2001
From: Jan Tuomi <jans.tuomi@gmail.com>
Date: Sat, 11 Nov 2023 23:13:43 +0200
Subject: Add function defs & calls

---
 asm/test_py_src.atk16_optimized | 161 ++++++++++++++++++++++++++++++++++++----
 1 file changed, 145 insertions(+), 16 deletions(-)

(limited to 'asm/test_py_src.atk16_optimized')

diff --git a/asm/test_py_src.atk16_optimized b/asm/test_py_src.atk16_optimized
index 4a65ec4..601dfad 100644
--- a/asm/test_py_src.atk16_optimized
+++ b/asm/test_py_src.atk16_optimized
@@ -58,28 +58,157 @@
   ldi gr_disabled_mode RB
   str RB RA
   jpi main
+@label text_mode
+  1
+@label graphics_mode_addr_p
+  23
+@label text_mem_addr_p
+  25
+@label int_1
+  104
+@label int_2
+  105
 @label func
   addi SP 1 SP
-  ldi ${SP - 3} RA
+  ldi vt_stack_addr RC
+  ldr RC RC
+  ldi 5 RD
+  add RC RD RC
+  ldr RC RC
+  spu RC
+  ldi vt_stack_addr RA
   ldr RA RA
-  ldi ${SP - 1} RB
-  str RA RB
-  ldi ${SP - 1} RA
+  ldi 7 RB
+  add RA RB RA
+  spo RB
+  str RB RA
+  ldi vt_stack_addr RA
   ldr RA RA
-  ldi ${SP - 1} RB
-  ldr RB RB
+  ldi 4 RB
   add RA RB RA
-  spu RA
-  subi SP 1 SP
-  rsr
+  ldi vt_stack_addr RC
+  ldr RC RC
+  ldi 7 RD
+  add RC RD RC
+  ldr RC RC
+  spu RC
+  ldi vt_stack_addr RC
+  ldr RC RC
+  ldi 7 RD
+  add RC RD RC
+  ldr RC RD
+  spo RC
+  add RC RD RB
+  mov RA SP
+  ldr RA RA
+  spu RB
+  jpr RA
 @label main
-  addi SP 1 SP
-  ldi 1 RA
+  addi SP 4 SP
+  ldi graphics_mode_addr_p RC
+  ldr RC RC
+  ldr RC RC
+  spu RC
+  ldi vt_stack_addr RA
+  ldr RA RA
+  ldi 1 RB
+  add RA RB RA
+  spo RB
+  str RB RA
+  ldi text_mem_addr_p RC
+  ldr RC RC
+  ldr RC RC
+  spu RC
+  ldi vt_stack_addr RA
+  ldr RA RA
+  ldi 2 RB
+  add RA RB RA
+  spo RB
+  str RB RA
+  ldi vt_stack_addr RA
+  ldr RA RA
+  ldi 1 RB
+  add RA RB RA
+  ldr RA RA
+  ldi text_mode RB
+  ldr RB RB
+  str RB RA
+  ldi 0 RC
+  spu RC
+  ldi 1 RC
+  spu RC
+  ldi 3 RC
+  spu RC
+  subi SP 3 RC
+  lpc RD
+  addi RD 3 RD
+  str RD RC
+  jpi func
+  ldi vt_stack_addr RA
+  ldr RA RA
+  ldi 3 RB
+  add RA RB RA
+  spo RB
+  str RB RA
+  ldi 0 RC
+  spu RC
+  ldi vt_stack_addr RA
+  ldr RA RA
+  ldi 0 RB
+  add RA RB RA
+  spo RB
+  str RB RA
+  ldi vt_stack_addr RA
+  ldr RA RA
+  ldi 2 RB
+  add RA RB RA
+  ldr RA RA
   spu RA
-  ldi 3 RA
+  ldi vt_stack_addr RA
+  ldr RA RA
+  ldi 0 RB
+  add RA RB RA
+  ldr RA RB
+  spo RA
+  add RA RB RA
+  ldi int_1 RB
+  ldr RB RB
+  str RB RA
+  ldi vt_stack_addr RC
+  ldr RC RC
+  ldi 0 RD
+  add RC RD RC
+  ldr RC RC
+  ldi 1 RD
+  add RC RD RC
+  spu RC
+  ldi vt_stack_addr RA
+  ldr RA RA
+  ldi 0 RB
+  add RA RB RA
+  spo RB
+  str RB RA
+  ldi vt_stack_addr RA
+  ldr RA RA
+  ldi 2 RB
+  add RA RB RA
+  ldr RA RA
   spu RA
-  csi func
+  ldi vt_stack_addr RA
+  ldr RA RA
+  ldi 0 RB
+  add RA RB RA
+  ldr RA RB
   spo RA
-  ldi ${SP - 1} RB
-  str RA RB
-  subi SP 1 SP
\ No newline at end of file
+  add RA RB RA
+  ldi int_2 RB
+  ldr RB RB
+  str RB RA
+@label while_test_3
+  ldi 1 RA
+  addi RA 0 RA
+  bri zero While_else_4
+  jpi While_test_3
+@label while_else_4
+@label while_end_5
+  subi SP 4 SP
\ No newline at end of file
-- 
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