From 69de37cdb25563f6cbd2a3c1a338b1e0dd47b3a4 Mon Sep 17 00:00:00 2001
From: Jan Tuomi <jan@jantuomi.fi>
Date: Tue, 18 Mar 2025 18:38:44 +0200
Subject: Start reworking fpga impl

---
 atk16_fpga/Makefile | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 atk16_fpga/Makefile

(limited to 'atk16_fpga/Makefile')

diff --git a/atk16_fpga/Makefile b/atk16_fpga/Makefile
new file mode 100644
index 0000000..cada068
--- /dev/null
+++ b/atk16_fpga/Makefile
@@ -0,0 +1,24 @@
+BIN ?= program.bin
+
+hardware.bin: top.v
+	apio verify
+	apio test
+	apio build
+
+.PHONY: hw
+hw: hardware.bin
+	apio upload
+
+.PHONY: sw
+sw: $(BIN)
+	iceprogduino -w -o 1M $(BIN)
+
+.PHONY: graph
+graph:
+	yosys -f verilog -p "show -format dot -colors 1 -prefix hardware top" -q top.v
+	dot -Tsvg hardware.dot -o hardware.svg
+	open -a LibreWolf hardware.svg
+
+.PHONY: clean
+clean:
+	apio clean
-- 
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