From 5636fc7373b51306c8a3b8ba703831f67fdbf685 Mon Sep 17 00:00:00 2001
From: Jan Tuomi <jan@jantuomi.fi>
Date: Fri, 27 Dec 2024 01:18:30 +0200
Subject: Implement opcodes, add tests

---
 atk16_fpga/mem_fsm.v | 23 +++++++----------------
 1 file changed, 7 insertions(+), 16 deletions(-)

(limited to 'atk16_fpga/mem_fsm.v')

diff --git a/atk16_fpga/mem_fsm.v b/atk16_fpga/mem_fsm.v
index d5419c5..051705e 100644
--- a/atk16_fpga/mem_fsm.v
+++ b/atk16_fpga/mem_fsm.v
@@ -1,11 +1,8 @@
 `default_nettype none
 
 `define ST_IDLE   3'd0
-`define ST_READ1  3'd1
-`define ST_READ2  3'd2
-`define ST_WRITE1 3'd4
-`define ST_WRITE2 3'd5
-`define ST_END    3'd7
+`define ST_READ   3'd1
+`define ST_WRITE  3'd2
 
 module mem_fsm(
     input clk,
@@ -23,7 +20,7 @@ module mem_fsm(
     bram bram_inst(
         .clk(clk),
         .addr(bram_addr),
-        .cs_n(0),
+        .cs_n(1'd0),
         .wr_n(~wr),
         .rd_n(~rd),
         .bram_data_in(data_in),
@@ -35,29 +32,23 @@ module mem_fsm(
             `ST_IDLE: begin
                 done <= 0;
                 if (~done && read_en) begin
-                    state <= `ST_READ1;
+                    state <= `ST_READ;
                     bram_addr <= addr;
                     rd <= 1;
                     wr <= 0;
                 end
                 else if (~done && write_en) begin
-                    state <= `ST_WRITE1;
+                    state <= `ST_WRITE;
                     bram_addr <= addr;
                     rd <= 0;
                     wr <= 1;
                 end
             end
-            `ST_READ1: begin
-                state <= `ST_READ2;
-            end
-            `ST_READ2: begin
+            `ST_READ: begin
                 state <= `ST_IDLE;
                 done <= 1;
             end
-            `ST_WRITE1: begin
-                state <= `ST_WRITE2;
-            end
-            `ST_WRITE2: begin
+            `ST_WRITE: begin
                 state <= `ST_IDLE;
                 done <= 1;
             end
-- 
cgit v1.3