From 69de37cdb25563f6cbd2a3c1a338b1e0dd47b3a4 Mon Sep 17 00:00:00 2001 From: Jan Tuomi Date: Tue, 18 Mar 2025 18:38:44 +0200 Subject: Start reworking fpga impl --- atk16_fpga/mmodel_sram.v | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 atk16_fpga/mmodel_sram.v (limited to 'atk16_fpga/mmodel_sram.v') diff --git a/atk16_fpga/mmodel_sram.v b/atk16_fpga/mmodel_sram.v new file mode 100644 index 0000000..c0e5a0b --- /dev/null +++ b/atk16_fpga/mmodel_sram.v @@ -0,0 +1,32 @@ +`default_nettype none `timescale 1 ns / 100 ps + +// This is a memory model of the SRAM chip on the iCE40HX8K-EVB. +// Relevant specs: +// - 256Kx16 capacity +// - 18-bit address bus, 16-bit data bus +// - 10 ns read or write cycle time +// - 3 ns output hold from address change +module mmodel_sram ( + input wire cs_n, + input wire wr_n, + input wire rd_n, + input wire [17:0] addr, + input wire [15:0] data_in, + output reg [15:0] data_out +); + reg [15:0] mem[0:262143]; // 256K x 16 memory + + always @(cs_n or wr_n or rd_n or addr or data_in) begin + if (cs_n == 1'b1) begin + data_out <= #3 16'hx; + end + if (cs_n == 1'b0 && wr_n == 1'b0) begin + mem[addr] <= #3 16'hx; + mem[addr] <= #7 data_in; + end + if (cs_n == 1'b0 && rd_n == 1'b0) begin + data_out <= #3 16'hx; + data_out <= #7 mem[addr]; + end + end +endmodule -- cgit v1.3