From 99203fb27559f91ff903690338af76f6f29cf52d Mon Sep 17 00:00:00 2001
From: Jan Tuomi <jan@jantuomi.fi>
Date: Thu, 2 Jan 2025 15:36:57 +0200
Subject: WIP flash bootload

---
 atk16_fpga/top.v | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'atk16_fpga/top.v')

diff --git a/atk16_fpga/top.v b/atk16_fpga/top.v
index 975a7f5..065d034 100644
--- a/atk16_fpga/top.v
+++ b/atk16_fpga/top.v
@@ -1,5 +1,8 @@
 `default_nettype none
 
+`define PH_COPY_IMG 1'b0
+`define PH_RUN_IMG  1'b1
+
 module top(
     input wire SYSCLK,
     input wire BUT1,
@@ -13,6 +16,8 @@ module top(
 
     input  [3:0] INT
 );
+    reg phase = `PH_COPY_IMG;
+
     cu cu_inst(
         .clk(SYSCLK),
         .rst(BUT1),
-- 
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