@use ext_std:*
@let sp RH
@let vector_table 0x10
@let vt_ISR0 0x10
@let vt_ISR1 0x11
@let vt_ISR2 0x12
@let vt_ISR3 0x13
@let vt_stack_addr 0x14
@let vt_term_pp_addr 0x15
@let vt_kb_pp_addr 0x16
@let vt_gr_mode_addr 0x17
@let vt_sprite_mem 0x18
@let vt_text_mem 0x19
@let stack_segment 0x8000
@let mmio_segment 0xE000
@let terminal_addr 0xE000
@let keyboard_addr 0xE001
@let gr_mode_addr 0xE002
@let sprite_mem 0xE800
@let text_mem 0xF800
@let gr_disabled_mode 0b00
@let gr_text_mode 0b01
@let gr_sprite_mode 0b10
@address 0x0
  ldi vt_stack_addr RA
  ldr RA SP
  jpi program_segment
@address vector_table
  keyboard_isr
  hlt_isr
  hlt_isr
  hlt_isr
  stack_segment
  terminal_addr
  keyboard_addr
  gr_mode_addr
  sprite_mem
  text_mem
@label hlt_isr
  ldi 0x55 RE
  hlt
@label keyboard_isr
  spu RA
  spu RB
  ldi vt_kb_pp_addr RA
  ldr RA RA
  ldr RA RA
  ldi vt_term_pp_addr RB
  ldr RB RB
  str RA RB
  spo RB
  spo RA
  rti
@label program_segment
  ldi vt_gr_mode_addr RA
  ldr RA RA
  ldi gr_disabled_mode RB
  str RB RA
  jpi main
@label text_mode
  1
@label graphics_mode_addr_p
  23
@label text_mem_addr_p
  25
@label int_1
  65
@label int_5
  26
@label nth_letter
  ldi vt_stack_addr RA
  ldr RA RA
  ldi 4 RB
  add RA RB RA
  ldr RA RA
  ldi int_1 RB
  ldr RB RB
  add RA RB RA
  spu RA
  ldi vt_stack_addr RA
  ldr RA RA
  ldi 3 RB
  add RA RB RA
  spo RB
  mov RA SP
  ldr RA RA
  spu RB
  jpr RA
@label main
  addi SP 3 SP
  ldi graphics_mode_addr_p RC
  ldr RC RC
  ldr RC RC
  spu RC
  ldi vt_stack_addr RA
  ldr RA RA
  ldi 0 RB
  add RA RB RA
  spo RB
  str RB RA
  ldi text_mem_addr_p RC
  ldr RC RC
  ldr RC RC
  spu RC
  ldi vt_stack_addr RA
  ldr RA RA
  ldi 1 RB
  add RA RB RA
  spo RB
  str RB RA
  ldi vt_stack_addr RA
  ldr RA RA
  ldi 0 RB
  add RA RB RA
  ldr RA RA
  ldi text_mode RB
  ldr RB RB
  str RB RA
  ldi 0 RC
  spu RC
  ldi vt_stack_addr RA
  ldr RA RA
  ldi 2 RB
  add RA RB RA
  spo RB
  str RB RA
  ldi 0b111111111 RG
@label while_test_2
  ldi vt_stack_addr RB
  ldr RB RB
  ldi 2 RC
  add RB RC RB
  ldr RB RB
  ldi int_5 RC
  ldr RC RC
  sub RB RC RB
  bri carry Compare_true_6
  ldi 0 RB
  spu RB
  jpi Compare_end_7
@label compare_true_6
  ldi 1 RB
  spu RB
@label compare_end_7
  spo RA
  addi RA 0 RA
  bri zero While_else_3
  ldi vt_stack_addr RA
  ldr RA RA
  ldi 1 RB
  add RA RB RA
  ldr RA RA
  spu RA
  ldi vt_stack_addr RA
  ldr RA RA
  ldi 2 RB
  add RA RB RA
  ldr RA RB
  spo RA
  add RA RB RA
  spu RA
  ldi 0 RA
  spu RA
  ldi vt_stack_addr RA
  ldr RA RA
  ldi 2 RB
  add RA RB RA
  ldr RA RA
  spu RA
  subi SP 2 RA
  lpc RB
  addi RB 3 RB
  str RB RA
  jpi nth_letter
  spo RB
  spo RA
  str RB RA
  ldi vt_stack_addr RC
  ldr RC RC
  ldi 2 RD
  add RC RD RC
  ldr RC RC
  ldi 1 RD
  add RC RD RC
  spu RC
  ldi vt_stack_addr RA
  ldr RA RA
  ldi 2 RB
  add RA RB RA
  spo RB
  str RB RA
  jpi While_test_2
@label while_else_3
@label while_end_4
@label while_test_8
  ldi 1 RA
  addi RA 0 RA
  bri zero While_else_9
  jpi While_test_8
@label while_else_9
@label while_end_10
  subi SP 3 SP