2 romContent Width 7 Comparator Bits 10 Const Value 798 Bits 10 intFormat dec Counter Bits 10 VDD rotation Tunnel rotation NetName PCLK Comparator Bits 10 Const Value 113 Bits 10 intFormat dec Comparator Bits 10 Const Value 16 Bits 10 intFormat dec NAnd Tunnel NetName HSYNC In Description Pixel clock Label PCLK Tunnel NetName PCLK In Description CPU clock Label CLK Tunnel NetName CLK RAMDualPort AddrBits 7 Label SPRITE MEM Bits 16 Text Description 8 bits tile pattern index 10 bits Y position 10 bits X position 1 bit H flip 1 bit V flip 1 bit behind background? (priority) 1 bit palette select = total 4 bytes per sprite x 64 sprites = 128 words Text Description 2**7 selector addresses for sprite mem, starting from 0x0800 In Label MMIO_IE In Label MMIO_OE Tunnel rotation NetName CLK In Description Data bus Label DBUS Bits 16 Tunnel NetName DBUS Tunnel rotation NetName DBUS Tunnel rotation NetName SMEMBUS In Description MMI/O selector Label MMIO_S Bits 13 Splitter Input Splitting 13 Output Splitting 11,1,1 And inverterConfig In_2 Tunnel rotation NetName SM_QUERY Ground Bits 11 Const Value 160 Bits 10 intFormat dec Sub Bits 10 Ground Comparator Bits 10 Const Value 523 Bits 10 intFormat dec Counter Bits 10 VDD rotation Comparator Bits 10 Const Value 10 Bits 10 intFormat dec Comparator Bits 10 Const Value 13 Bits 10 intFormat dec Tunnel NetName VSYNC NAnd Const Value 45 Bits 10 intFormat dec Sub Bits 10 Ground Splitter Input Splitting 10 Output Splitting 1,9 Splitter Input Splitting 10 Output Splitting 1,9 Text Description Div 2 Text Description Div 2 RAMDualPort AddrBits 9 Label SCAN BUFFER Bits 4 Tunnel rotation NetName X Splitter mirror true Input Splitting 4 Output Splitting 1*4 atk16_ppu_palette.dig Splitter Input Splitting 1,1 Output Splitting 2 Splitter Input Splitting 1,1 Output Splitting 2 Splitter Input Splitting 1,1 Output Splitting 2 Tunnel NetName PR Tunnel NetName PG Tunnel NetName PB Ground rotation Bits 4 Ground rotation Counter Tunnel rotation NetName PCLK VDD Ground Text Description TODO Tunnel rotation NetName SMEMBUS Ground rotation Bits 7 Tunnel NetName X Tunnel NetName Y Text Description TODO: 8x8x4 tile pattern memory VDD rotation Probe Label SCAN BUF Out Label PR Bits 2 Out Label PG Bits 2 Out Label PB Bits 2 Out Label HSYNC Out Label VSYNC Bits 2 Tunnel rotation NetName PB Tunnel rotation NetName PR Tunnel rotation NetName PG Tunnel rotation NetName HSYNC Tunnel rotation NetName VSYNC