2 romContent Width 6 Out Label PR Bits 2 Out Label PG Bits 2 Out Label PB Bits 2 In Description MMI/O selector Label MMIO_S Bits 13 In Label MMIO_IE In Label MMIO_OE Tunnel NetName MMIO_IE Tunnel NetName MMIO_OE Tunnel NetName MMIO_S In Description Pixel clock Label PCLK Tunnel NetName PCLK In Description CPU clock Label CLK Tunnel NetName CLK In Description Data bus Label DBUS Bits 16 Tunnel NetName DBUS In Description X pixel Label X Bits 9 Tunnel NetName X In Description Y pixel Label Y Bits 8 RAMDualPort AddrBits 11 Label TEXTMEM Bits 8 Tunnel rotation NetName Y Splitter Input Splitting 8 Output Splitting 3,5 Splitter Input Splitting 5,6 Output Splitting 11 Tunnel rotation NetName TY Tunnel rotation NetName TX Tunnel rotation NetName CCOLOR Splitter Input Splitting 1,1 Output Splitting 2 Ground rotation Bits 8 Ground rotation VDD rotation Tunnel NetName CHAR_S Tunnel NetName Y Tunnel NetName TY Tunnel NetName CY Counter Bits 3 And inverterConfig In_1 In_2 Inputs 3 Splitter Input Splitting 3 Output Splitting 1,1,1 Tunnel rotation NetName PCLK VDD rotation Counter Bits 6 Tunnel NetName CX VDD rotation Ground rotation Tunnel NetName TX Tunnel NetName COVF Not Tunnel rotation NetName COVF Probe intFormat dec EEPROM AddrBits 11 Label CHARMEM Bits 8 Data 6,9,9,f,9,9,9,0,3,5,5,7,9,9,f,0,6,9,1,1,1,9,6,0,f,1,1,3,1,1,f ,0,f,1,1,3,1,1,1,0,6,9,1,1,d,9,6,0,9,9,f,4*9,0,7,5*2,7,0,e,4*8 ,9,6,0,9,5,3,5,5,9,9,0,6*1,f,0,9,f,f,4*9,0,9,b,b,d,d,9,9,0,6,5*9 ,6,0,7,9,9,7,1,1,1,0,6,9,9,9,d,e,8,0,7,9,9,7,3,5,9,0,6,9,1,6,8 ,9,6,0,7,6*2,0,6*9,e,0,6*9,6,0,4*9,f,f,9,0,9,9,6,4*9,0,9,9,9,e ,8,9,e,0,f,8,8,4,2,1,f intFormat bin Ground rotation VDD rotation VDD rotation Splitter Input Splitting 3,8 Output Splitting 11 Tunnel rotation NetName CHAR_S Tunnel rotation NetName CY BitSelector Selector Bits 3 Tunnel NetName CX Tunnel NetName CCOLOR Probe intFormat bin Probe Probe