Add stuff, refactor

1 files changed, 160 insertions, 6 deletions

diff --git a/atk16_asm/asm_ops.py b/atk16_asm/asm_ops.py
index 885c275..394a643 100644
--- a/atk16_asm/asm_ops.py
+++ b/atk16_asm/asm_ops.py
@@ -1,6 +1,10 @@
 from typing import Callable
-from asm_eval import *
 from dataclasses import dataclass
+from .asm_eval import *
+
+ExpandResult = list[list[str]]
+ExpandFn = Callable[..., ExpandResult]
+OpExpansionDict = dict[str, ExpandFn]
 
 @dataclass
 class Meta:
@@ -130,14 +134,131 @@ operations: OpWordDict = {
   "hlt": make_hlt,
 }
 
-ExpandResult = list[list[str]]
-ExpandFn = Callable[..., ExpandResult]
-OpExpansionDict = dict[str, ExpandFn]
-
 def expand_id(*parts: str) -> ExpandResult:
   return [list(parts)]
 
-default_expansions: OpExpansionDict = {
+def expand_add(left: str, right: str, target: str) -> ExpandResult:
+  return [["alr", "al_plus", left, right, target]]
+
+def expand_sub(left: str, right: str, target: str) -> ExpandResult:
+  return [["alr", "al_minus", left, right, target]]
+
+def expand_addi(left: str, imm: str, target: str) -> ExpandResult:
+  return [["ali", "al_plus", left, imm, target]]
+
+def expand_subi(left: str, imm: str, target: str) -> ExpandResult:
+  return [["ali", "al_minus", left, imm, target]]
+
+def expand_not(reg: str, target: str) -> ExpandResult:
+  return [["alr", "al_xor", reg, "0xFFFF", target]]
+
+def expand_noti(imm: str, target: str) -> ExpandResult:
+  return [["ali", "al_xor", imm, "0xFFFF", target]]
+
+def expand_and(left: str, right: str, target: str) -> ExpandResult:
+  return [["alr", "al_and", left, right, target]]
+
+def expand_andi(left: str, imm: str, target: str) -> ExpandResult:
+  return [["ali", "al_and", left, imm, target]]
+
+def expand_or(left: str, right: str, target: str) -> ExpandResult:
+  return [["alr", "al_or", left, right, target]]
+
+def expand_ori(left: str, imm: str, target: str) -> ExpandResult:
+  return [["ali", "al_or", left, imm, target]]
+
+def expand_xor(left: str, imm: str, target: str) -> ExpandResult:
+  return [["alr", "al_xor", left, imm, target]]
+
+def expand_xori(left: str, right: str, target: str) -> ExpandResult:
+  return [["ali", "al_xor", left, right, target]]
+
+def expand_sll(left: str, right: str, target: str) -> ExpandResult:
+  return [["alr", "al_sll", left, right, target]]
+
+def expand_slr(left: str, right: str, target: str) -> ExpandResult:
+  return [["alr", "al_slr", left, right, target]]
+
+def expand_sar(left: str, right: str, target: str) -> ExpandResult:
+  return [["alr", "al_sar", left, right, target]]
+
+def expand_slli(left: str, imm: str, target: str) -> ExpandResult:
+  return [["ali", "al_sll", left, imm, target]]
+
+def expand_slri(left: str, imm: str, target: str) -> ExpandResult:
+  return [["ali", "al_slr", left, imm, target]]
+
+def expand_sari(left: str, imm: str, target: str) -> ExpandResult:
+  return [["ali", "al_sar", left, imm, target]]
+
+def expand_inc(reg: str) -> ExpandResult:
+  return [["ali", "al_plus", reg, "1", reg]]
+
+def expand_dec(reg: str) -> ExpandResult:
+  return [["ali", "al_minus", reg, "1", reg]]
+
+def expand_mov(from_reg: str, to_reg: str) -> ExpandResult:
+  return [["ali", "al_plus", from_reg, "0", to_reg]]
+
+def expand_nop() -> ExpandResult:
+  return [["ali", "al_plus", "RA", "0", "RA"]]
+
+def expand_spu(reg: str) -> ExpandResult:
+  return [["str", reg, "SP"]] + expand_inc("SP")
+
+def expand_spo(reg: str) -> ExpandResult:
+  return expand_dec("SP") + [["ldr", "SP", reg]]
+
+def expand_sinc(imm: str) -> ExpandResult:
+  return expand_addi("SP", imm, "SP")
+
+def expand_sdec(imm: str) -> ExpandResult:
+  return expand_subi("SP", imm, "SP")
+
+def expand_csr(addr_reg: str, stratch_reg: str) -> ExpandResult:
+  return [
+    ["lpc", stratch_reg],
+    *expand_addi(stratch_reg, "4", stratch_reg),
+    *expand_spu(stratch_reg),
+    ["jpr", addr_reg]
+  ]
+
+def expand_csi(addr_imm: str, stratch_reg: str) -> ExpandResult:
+  return [
+    ["lpc", stratch_reg],
+    *expand_addi(stratch_reg, "4", stratch_reg),
+    *expand_spu(stratch_reg),
+    ["jpi", addr_imm]
+  ]
+
+def expand_rsr(stratch_reg: str) -> ExpandResult:
+  return expand_spo(stratch_reg) + [["jpr", stratch_reg]]
+
+
+def stack_stash(*rs: str) -> ExpandResult:
+  result: ExpandResult = []
+  for r in rs:
+    result += expand_spu(r)
+
+  return result
+
+def stack_restore(*rs: str) -> ExpandResult:
+  result: ExpandResult = []
+  for r in rs:
+    prefix = expand_spu(r)
+    result = prefix + result
+
+  return result
+
+def set_graphics_mode(mode: str) -> ExpandResult:
+  return [
+    ["ldi", "vt_gr_mode_addr", "RA"],
+    ["ldr", "RA", "RA"],
+    ["ldi", mode, "RB"],
+    ["str", "RB", "RA"],
+  ]
+
+expansions: OpExpansionDict = {
   "alr": lambda *args: expand_id("alr", *args),
   "ali": lambda *args: expand_id("ali", *args),
   "ldr": lambda *args: expand_id("ldr", *args),
@@ -150,5 +271,38 @@ default_expansions: OpExpansionDict = {
   "lpc": lambda *args: expand_id("lpc", *args),
   "rti": lambda *args: expand_id("rti", *args),
   "hlt": lambda *args: expand_id("hlt", *args),
+
+  "add": expand_add,
+  "sub": expand_sub,
+  "addi": expand_addi,
+  "subi": expand_subi,
+  "not": expand_not,
+  "noti": expand_noti,
+  "and": expand_and,
+  "andi": expand_andi,
+  "or": expand_or,
+  "ori": expand_ori,
+  "xor": expand_xor,
+  "xori": expand_xori,
+  "sll": expand_sll,
+  "slr": expand_slr,
+  "sar": expand_sar,
+  "slli": expand_slli,
+  "slri": expand_slri,
+  "sari": expand_sari,
+  "inc": expand_inc,
+  "dec": expand_dec,
+  "mov": expand_mov,
+  "nop": expand_nop,
+  "spu": expand_spu,
+  "spo": expand_spo,
+  "sinc": expand_sinc,
+  "sdec": expand_sdec,
+  "csr": expand_csr,
+  "csi": expand_csi,
+  "rsr": expand_rsr,
+  "stack_stash": stack_stash,
+  "stack_restore": stack_restore,
+  "set_graphics_mode": set_graphics_mode,
 }