Fix and test interrupts

1 files changed, 131 insertions, 97 deletions

diff --git a/atk16_fpga/cu_tb.v b/atk16_fpga/cu_tb.v
index 8c8ec10..d472ac3 100644
--- a/atk16_fpga/cu_tb.v
+++ b/atk16_fpga/cu_tb.v
@@ -40,7 +40,8 @@ module cu_tb();
     always #5 clk = ~clk;  // 100 MHz clock
 
     reg failed;
-    reg [15:0] expected;
+    reg [15:0] expected, expected2;
+    reg [31:0] test_num = 0;
     initial begin
         failed = 0;
         $dumpfile(`DUMPSTR(`VCD_OUTPUT));
@@ -62,12 +63,12 @@ module cu_tb();
         expected = 16'd30;
 
         #200 if (dut.regbank[2] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m ALR ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] ALR ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m ALR not working, target reg contains %04h, expected %04h", dut.regbank[2], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] ALR not working, target reg contains %04h, expected %04h", test_num, dut.regbank[2], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test ALI
         dut.regbank[0] = 16'd10;
@@ -75,12 +76,12 @@ module cu_tb();
         expected = 16'd17;
 
         #200 if (dut.regbank[2] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m ALI ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] ALI ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m ALI not working, target reg contains %04h, expected %04h", dut.regbank[2], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] ALI not working, target reg contains %04h, expected %04h", test_num, dut.regbank[2], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test LDR, absolute addressing
         sram_inst.mem[16'd100] = 16'hffff;
@@ -89,12 +90,12 @@ module cu_tb();
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m LDR direct absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] LDR direct absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m LDR direct absolute not working, target reg contains %04h, expected %04h", dut.regbank[0], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] LDR direct absolute not working, target reg contains %04h, expected %04h", test_num, dut.regbank[0], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test LDR, relative addressing
         sram_inst.mem[16'd10] = 16'hffff;
@@ -103,12 +104,12 @@ module cu_tb();
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m LDR direct relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] LDR direct relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m LDR direct relative not working, target reg contains %04h, expected %04h", dut.regbank[0], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] LDR direct relative not working, target reg contains %04h, expected %04h", test_num, dut.regbank[0], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test LDR, absolute addressing, indirect
         sram_inst.mem[16'd100] = 16'd200;
@@ -118,12 +119,12 @@ module cu_tb();
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m LDR indirect absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] LDR indirect absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m LDR indirect absolute not working, target reg contains %04h, expected %04h", dut.regbank[0], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] LDR indirect absolute not working, target reg contains %04h, expected %04h", test_num, dut.regbank[0], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test LDR, relative addressing, indirect
         sram_inst.mem[16'd10] = 16'd20;
@@ -133,12 +134,12 @@ module cu_tb();
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m LDR indirect relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] LDR indirect relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m LDR indirect relative not working, target reg contains %04h, expected %04h", dut.regbank[0], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] LDR indirect relative not working, target reg contains %04h, expected %04h", test_num, dut.regbank[0], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test STR, absolute addressing, direct
         dut.regbank[0] = 16'hfafa;
@@ -147,12 +148,12 @@ module cu_tb();
         expected = 16'hfafa;
 
         #200 if (sram_inst.mem[16'd100] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m STR direct absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] STR direct absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR direct absolute not working, memory location contains %04h, expected %04h", sram_inst.mem[16'd100], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] STR direct absolute not working, memory location contains %04h, expected %04h", test_num, sram_inst.mem[16'd100], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test STR, relative addressing, direct
         dut.regbank[0] = 16'hafaf;
@@ -161,12 +162,12 @@ module cu_tb();
         expected = 16'hafaf;
 
         #200 if (sram_inst.mem[16'd10] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m STR direct relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] STR direct relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR direct relative not working, memory location contains %04h, expected %04h", sram_inst.mem[16'd10], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] STR direct relative not working, memory location contains %04h, expected %04h", test_num, sram_inst.mem[16'd10], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test STR, absolute addressing, indirect
         dut.regbank[0] = 16'hfafa;
@@ -176,12 +177,12 @@ module cu_tb();
         expected = 16'hfafa;
 
         #200 if (sram_inst.mem[16'd200] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m STR indirect absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] STR indirect absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR indirect absolute not working, memory location contains %04h, expected %04h", sram_inst.mem[16'd200], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] STR indirect absolute not working, memory location contains %04h, expected %04h", test_num, sram_inst.mem[16'd200], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test STR, relative addressing, indirect
         dut.regbank[0] = 16'hafaf;
@@ -192,24 +193,24 @@ module cu_tb();
         expected = 16'hafaf;
 
         #200 if (sram_inst.mem[16'd20] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m STR indirect relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] STR indirect relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR indirect relative not working, memory location contains %04h, expected %04h", sram_inst.mem[16'd20], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] STR indirect relative not working, memory location contains %04h, expected %04h", test_num, sram_inst.mem[16'd20], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test LDI, absolute addressing, direct
         sram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd123, 1'd1, 1'd1 }; // LDI RA, 1, absolute, direct
         expected = 16'd123;
 
         #200 if (dut.regbank[0] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m LDI direct absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] LDI direct absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m LDI direct absolute not working, target reg contains %04h, expected %04h", dut.regbank[0], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] LDI direct absolute not working, target reg contains %04h, expected %04h", test_num, dut.regbank[0], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test LDI, relative addressing, direct
         sram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd1 }; // LDI RA, 1, relative, direct
@@ -217,12 +218,12 @@ module cu_tb();
         expected = 16'd130;
 
         #200 if (dut.regbank[0] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m LDI direct relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] LDI direct relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m LDI direct relative not working, target reg contains %04h, expected %04h", dut.regbank[0], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] LDI direct relative not working, target reg contains %04h, expected %04h", test_num, dut.regbank[0], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test LDI, absolute addressing, indirect
         sram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd50, 1'd1, 1'd0 }; // LDI RA, 1, absolute, indirect
@@ -230,12 +231,12 @@ module cu_tb();
         expected = 16'd123;
 
         #200 if (dut.regbank[0] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m LDI indirect absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] LDI indirect absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m LDI indirect absolute not working, target reg contains %04h, expected %04h", dut.regbank[0], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] LDI indirect absolute not working, target reg contains %04h, expected %04h", test_num, dut.regbank[0], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test LDI, relative addressing, indirect
         sram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd0 }; // LDI RA, 1, relative, indirect
@@ -244,12 +245,12 @@ module cu_tb();
         expected = 16'd123;
 
         #200 if (dut.regbank[0] == expected) begin
-            $display("\033[0;32m[PASS]\033[0m LDI indirect relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] LDI indirect relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m LDI indirect relative not working, target reg contains %04h, expected %04h", dut.regbank[0], expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] LDI indirect relative not working, target reg contains %04h, expected %04h", test_num, dut.regbank[0], expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test JPR, absolute addressing, direct
         dut.regbank[0] = 16'd100;
@@ -258,12 +259,12 @@ module cu_tb();
         expected = 16'd101; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m JPR direct absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] JPR direct absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m JPR direct absolute not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] JPR direct absolute not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test JPR, relative addressing, direct
         dut.regbank[0] = 16'd50;
@@ -272,12 +273,12 @@ module cu_tb();
         expected = 16'd51; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m JPR direct relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] JPR direct relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m JPR direct relative not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] JPR direct relative not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test JPR, absolute addressing, indirect
         dut.regbank[0] = 16'd100;
@@ -287,12 +288,12 @@ module cu_tb();
         expected = 16'd201; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m JPR indirect absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] JPR indirect absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m JPR indirect absolute not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] JPR indirect absolute not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test JPR, relative addressing, indirect
         dut.regbank[0] = 16'd50;
@@ -303,12 +304,12 @@ module cu_tb();
         expected = 16'd101; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m JPR indirect relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] JPR indirect relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m JPR indirect relative not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] JPR indirect relative not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test JPI, absolute addressing, direct
         sram_inst.mem[16'd0] = { 4'b0110, 1'd1, 1'd1, 10'd123 }; // JPI 123, absolute, direct
@@ -316,12 +317,12 @@ module cu_tb();
         expected = 16'd124; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m JPI direct absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] JPI direct absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m JPI direct absolute not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] JPI direct absolute not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test JPI, relative addressing, direct
         sram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd1, -10'd20 }; // JPI -20, relative, direct
@@ -330,12 +331,12 @@ module cu_tb();
         expected = 16'd11; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m JPI direct relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] JPI direct relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m JPI direct relative not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] JPI direct relative not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test JPI, absolute addressing, indirect
         sram_inst.mem[16'd10] = { 4'b0110, 1'd1, 1'd0, 10'd50 }; // JPI 50, absolute, indirect
@@ -345,12 +346,12 @@ module cu_tb();
         expected = 16'd124; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m JPI indirect absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] JPI indirect absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m JPI indirect absolute not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] JPI indirect absolute not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test JPI, relative addressing, indirect
         sram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd0, -10'd20 }; // JPI -20, relative, indirect
@@ -360,12 +361,12 @@ module cu_tb();
         expected = 16'd51; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m JPI indirect relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] JPI indirect relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m JPI indirect relative not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] JPI indirect relative not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test BRR, absolute addressing, direct, true branch
         dut.regbank[0] = 16'd100;
@@ -377,12 +378,12 @@ module cu_tb();
         expected = 16'd111; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m BRR direct absolute true ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] BRR direct absolute true ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m BRR direct absolute true not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] BRR direct absolute true not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test BRR, absolute addressing, direct, false branch
         dut.regbank[0] = 16'd100;
@@ -394,12 +395,12 @@ module cu_tb();
         expected = 16'd3; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m BRR direct absolute false ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] BRR direct absolute false ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m BRR direct absolute false not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] BRR direct absolute false not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test BRR, relative addressing, direct
         dut.regbank[0] = 16'd100;
@@ -412,12 +413,12 @@ module cu_tb();
         expected = 16'd121; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m BRR direct relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] BRR direct relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m BRR direct relative not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] BRR direct relative not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test BRR, absolute addressing, indirect
         dut.regbank[0] = 16'd100;
@@ -430,12 +431,12 @@ module cu_tb();
         expected = 16'd201; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m BRR indirect absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] BRR indirect absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m BRR indirect absolute not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] BRR indirect absolute not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test BRR, relative addressing, indirect
         dut.regbank[0] = 16'd100;
@@ -449,12 +450,12 @@ module cu_tb();
         expected = 16'd131; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m BRR indirect relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] BRR indirect relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m BRR indirect relative not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] BRR indirect relative not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test BRI, absolute addressing, direct, true branch
         dut.regbank[0] = 16'd100;
@@ -465,12 +466,12 @@ module cu_tb();
         expected = 16'd101; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m BRI direct absolute true ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] BRI direct absolute true ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m BRI direct absolute true not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] BRI direct absolute true not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test BRI, absolute addressing, direct, false branch
         dut.regbank[0] = 16'd100;
@@ -481,12 +482,12 @@ module cu_tb();
         expected = 16'd3; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m BRI direct absolute false ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] BRI direct absolute false ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m BRI direct absolute false not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] BRI direct absolute false not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test BRI, relative addressing, direct
         dut.regbank[0] = 16'd100;
@@ -498,12 +499,12 @@ module cu_tb();
         expected = 16'd21; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m BRI direct relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] BRI direct relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m BRI direct relative not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] BRI direct relative not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test BRI, absolute addressing, indirect
         dut.regbank[0] = 16'd100;
@@ -515,12 +516,12 @@ module cu_tb();
         expected = 16'd201; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m BRI indirect absolute ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] BRI indirect absolute ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m BRI indirect absolute not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] BRI indirect absolute not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         // test BRI, relative addressing, indirect
         dut.regbank[0] = 16'd100;
@@ -533,12 +534,45 @@ module cu_tb();
         expected = 16'd131; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
-            $display("\033[0;32m[PASS]\033[0m BRI indirect relative ok");
+            $display("\033[0;32m[PASS]\033[0m [%0d] BRI indirect relative ok", test_num);
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m BRI indirect relative not working, PC contains %04h, expected: %04h", dut.pc, expected);
+            $display("\033[0;31m[FAIL]\033[0m [%0d] BRI indirect relative not working, PC contains %04h, expected: %04h", test_num, dut.pc, expected);
             failed = 1;
         end
-        rst = 1; #10 rst = 0; #10
+        rst = 1; #10 rst = 0; #10 test_num++;
+
+        // test interrupt handling
+        sram_inst.mem[16'd0] = { 4'b0001, 3'b0, 3'b0, 3'b0, 3'b0 }; // NOP (add imm zero)
+        sram_inst.mem[16'h10] = { 4'b1111, 12'd0 }; // HLT
+        expected  = 16'h11;
+        expected2 = 16'd0;
+        #5
+        int_lines = 4'b1001; // set interrupts
+
+        #200 if (dut.pc == expected && dut.int_pc == expected2) begin
+            $display("\033[0;32m[PASS]\033[0m [%0d] interrupt jump ok", test_num);
+        end else begin
+            $display("\033[0;31m[FAIL]\033[0m [%0d] interrupt jump not working, PC contains %04h (expected: %04h), int_pc contains %04h (expected: %04h)", test_num, dut.pc, expected, dut.int_pc, expected2);
+            failed = 1;
+        end
+        rst = 1; #10 rst = 0; #10 test_num++;
+
+        // test RTI
+        dut.int_en = 1'b0;
+        dut.pc = 16'h10;
+        dut.int_pc = 16'd1;
+        sram_inst.mem[16'h10] = { 4'b1010, 12'd0 }; // RTI
+        sram_inst.mem[16'd1] = { 4'b1111, 12'd0 }; // HLT
+        expected = 16'd2; // PC ends up at &HLT + 1
+        expected2 = 1'b1;
+
+        #200 if (dut.pc == expected && dut.int_en == expected2) begin
+            $display("\033[0;32m[PASS]\033[0m [%0d] interrupt return ok", test_num);
+        end else begin
+            $display("\033[0;31m[FAIL]\033[0m [%0d] interrupt return not working, PC contains %04h (expected: %04h), int_en contains %01b (expected: %01b)", test_num, dut.pc, expected, dut.int_en, expected2);
+            failed = 1;
+        end
+        rst = 1; #10 rst = 0; #10 test_num++;
 
         #200
         if (failed) begin