Develop fpga

1 files changed, 8 insertions, 10 deletions

diff --git a/atk16_fpga/top.v b/atk16_fpga/top.v
index c456b31..386d6e3 100644
--- a/atk16_fpga/top.v
+++ b/atk16_fpga/top.v
@@ -1,18 +1,16 @@
+`default_nettype none
+
 module top(
     input wire SYSCLK,
+    input wire BUT1,
     output wire LED1
 );
 
-    assign LED1 = SYSCLK;
-
-    wire [15:0] result;
-    wire [3:0]  flags;
-    alu alu_inst(
-        .sel(3'd0),
-        .a(16'd0),
-        .b(16'd0),
-        .result(result),
-        .flags(flags)
+    cu cu_inst(
+        .clk(SYSCLK),
+        .rst(BUT1)
     );
 
+    assign LED1 = BUT1;
+
 endmodule