Use SRAM instead of BRAM in CU

3 files changed, 224 insertions, 193 deletions

diff --git a/atk16_fpga/cu.v b/atk16_fpga/cu.v
index ce8998b..e68a3d5 100644
--- a/atk16_fpga/cu.v
+++ b/atk16_fpga/cu.v
@@ -67,11 +67,6 @@ module cu(
     input wire rst,
     input wire [3:0] int_lines
 );
-    reg  [2:0]  alu_sel;
-    reg  [15:0] alu_a;
-    reg  [15:0] alu_b;
-    wire [15:0] alu_result;
-    wire [3:0]  alu_flags;
     reg  [15:0] regbank [0:7];
     reg  [15:0] decoded_tmp;
     reg  [2:0]  phase = `PH_RESET;
@@ -87,18 +82,22 @@ module cu(
     reg  [15:0] mem_addr;
     reg  [15:0] mem_data_in;
     reg  mem_read_en, mem_write_en;
-    wire mem_done;
     wire [15:0] mem_data_out;
-    bram_fsm bram_fsm_inst(
-        .clk(clk),
-        .addr(mem_addr),
+    reg  mem_waiting = 0;
+    sram sram_inst(
+        .cs_n(1'd0),
+        .wr_n(~mem_write_en),
+        .rd_n(~mem_read_en),
+        .addr({ 2'd0, mem_addr }),
         .data_in(mem_data_in),
-        .read_en(mem_read_en),
-        .write_en(mem_write_en),
-        .data_out(mem_data_out),
-        .done(mem_done)
+        .data_out(mem_data_out)
     );
 
+    reg  [2:0]  alu_sel;
+    reg  [15:0] alu_a;
+    reg  [15:0] alu_b;
+    wire [15:0] alu_result;
+    wire [3:0]  alu_flags;
     alu alu_inst(
         .sel(alu_sel),
         .a(alu_a),
@@ -172,14 +171,16 @@ module cu(
 
         // Fetch stage
         else if (phase == `PH_FETCH) begin
-            mem_read_en  <= 1;
-            mem_addr     <= pc;
-
-            if (mem_done) begin
+            if (~mem_waiting) begin
+                mem_read_en  <= 1;
+                mem_addr     <= pc;
+                mem_waiting  <= 1;
+            end else begin
                 mem_read_en  <= 0;
                 ir           <= mem_data_out;
                 phase        <= `PH_DECODE;
                 pc           <= pc + 16'd1;
+                mem_waiting  <= 0;
             end
         end
 
@@ -211,23 +212,27 @@ module cu(
                         phase <= `PH_EXECUTE;
                     end
                     else if (ir[1] == 1 && ir[0] == 0) begin  // addressing mode: absolute, indirect
-                        mem_read_en    <= 1;
-                        mem_addr       <= regbank[ir[8:6]];
-
-                        if (mem_done) begin
-                            decoded_tmp       <= mem_data_out;
-                            mem_read_en       <= 0;
-                            phase             <= `PH_EXECUTE;
+                        if (~mem_waiting) begin
+                            mem_read_en    <= 1;
+                            mem_addr       <= regbank[ir[8:6]];
+                            mem_waiting    <= 1;
+                        end else begin
+                            decoded_tmp    <= mem_data_out;
+                            mem_read_en    <= 0;
+                            phase          <= `PH_EXECUTE;
+                            mem_waiting    <= 0;
                         end
                     end
                     else if (ir[1] == 0 && ir[0] == 0) begin // addressing mode: pc relative, indirect
-                        mem_read_en    <= 1;
-                        mem_addr       <= pc + regbank[ir[8:6]] - 1;
-
-                        if (mem_done) begin
-                            decoded_tmp       <= mem_data_out;
-                            mem_read_en       <= 0;
-                            phase             <= `PH_EXECUTE;
+                        if (~mem_waiting) begin
+                            mem_read_en    <= 1;
+                            mem_addr       <= pc + regbank[ir[8:6]] - 1;
+                            mem_waiting    <= 1;
+                        end else begin
+                            decoded_tmp    <= mem_data_out;
+                            mem_read_en    <= 0;
+                            phase          <= `PH_EXECUTE;
+                            mem_waiting    <= 0;
                         end
                     end
                 end
@@ -246,23 +251,27 @@ module cu(
                         phase <= `PH_EXECUTE;
                     end
                     else if (ir[1] == 1 && ir[0] == 0) begin  // addressing mode: absolute, indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= regbank[ir[8:6]];
-
-                        if (mem_done) begin
-                            decoded_tmp  <= mem_data_out;
-                            mem_read_en  <= 0;
-                            phase        <= `PH_EXECUTE;
+                        if (~mem_waiting) begin
+                            mem_read_en    <= 1;
+                            mem_addr       <= regbank[ir[8:6]];
+                            mem_waiting    <= 1;
+                        end else begin
+                            decoded_tmp    <= mem_data_out;
+                            mem_read_en    <= 0;
+                            phase          <= `PH_EXECUTE;
+                            mem_waiting    <= 0;
                         end
                     end
                     else if (ir[1] == 0 && ir[0] == 0) begin // addressing mode: pc relative, indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= pc + regbank[ir[8:6]] - 1;
-
-                        if (mem_done) begin
-                            decoded_tmp  <= mem_data_out;
-                            mem_read_en  <= 0;
-                            phase        <= `PH_EXECUTE;
+                        if (~mem_waiting) begin
+                            mem_read_en    <= 1;
+                            mem_addr       <= pc + regbank[ir[8:6]] - 1;
+                            mem_waiting    <= 1;
+                        end else begin
+                            decoded_tmp    <= mem_data_out;
+                            mem_read_en    <= 0;
+                            phase          <= `PH_EXECUTE;
+                            mem_waiting    <= 0;
                         end
                     end
                 end
@@ -292,23 +301,27 @@ module cu(
                         phase       <= `PH_FETCH;
                     end
                     else if (ir[11] == 1 && ir[10] == 0) begin // addressing mode: absolute, indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= regbank[ir[9:6]];
-
-                        if (mem_done) begin
+                        if (~mem_waiting) begin
+                            mem_read_en  <= 1;
+                            mem_addr     <= regbank[ir[9:6]];
+                            mem_waiting  <= 1;
+                        end else begin
                             pc          <= mem_data_out;
                             mem_read_en <= 0;
                             phase       <= `PH_FETCH;
+                            mem_waiting <= 0;
                         end
                     end
                     else if (ir[11] == 0 && ir[10] == 0) begin // addressing mode: pc relative, indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= pc + regbank[ir[9:6]] - 1;
-
-                        if (mem_done) begin
+                        if (~mem_waiting) begin
+                            mem_read_en  <= 1;
+                            mem_addr     <= pc + regbank[ir[9:6]] - 1;
+                            mem_waiting  <= 1;
+                        end else begin
                             pc          <= mem_data_out;
                             mem_read_en <= 0;
                             phase       <= `PH_FETCH;
+                            mem_waiting <= 0;
                         end
                     end
                 end
@@ -325,23 +338,27 @@ module cu(
                         phase       <= `PH_FETCH;
                     end
                     else if (ir[11] == 1 && ir[10] == 0) begin // addressing mode: absolute, indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= {6'd0, ir[9:0]};
-
-                        if (mem_done) begin
+                        if (~mem_waiting) begin
+                            mem_read_en  <= 1;
+                            mem_addr     <= {6'd0, ir[9:0]};
+                            mem_waiting  <= 1;
+                        end else begin
                             pc          <= mem_data_out;
                             mem_read_en <= 0;
                             phase       <= `PH_FETCH;
+                            mem_waiting <= 0;
                         end
                     end
                     else if (ir[11] == 0 && ir[10] == 0) begin // addressing mode: pc relative, indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= pc + {{6{ir[9]}}, ir[9:0]} - 1;
-
-                        if (mem_done) begin
+                        if (~mem_waiting) begin
+                            mem_read_en  <= 1;
+                            mem_addr     <= pc + {{6{ir[9]}}, ir[9:0]} - 1;
+                            mem_waiting  <= 1;
+                        end else begin
                             pc          <= mem_data_out;
                             mem_read_en <= 0;
                             phase       <= `PH_FETCH;
+                            mem_waiting <= 0;
                         end
                     end
                 end
@@ -359,23 +376,27 @@ module cu(
                         phase       <= `PH_EXECUTE;
                     end
                     else if (ir[11] == 1 && ir[10] == 0) begin // addressing mode: absolute, indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= regbank[ir[7:5]];
-
-                        if (mem_done) begin
+                        if (~mem_waiting) begin
+                            mem_read_en  <= 1;
+                            mem_addr     <= regbank[ir[7:5]];
+                            mem_waiting  <= 1;
+                        end else begin
                             decoded_tmp <= mem_data_out;
                             mem_read_en <= 0;
                             phase       <= `PH_EXECUTE;
+                            mem_waiting <= 0;
                         end
                     end
                     else if (ir[11] == 0 && ir[10] == 0) begin // addressing mode: pc relative, indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= pc + regbank[ir[7:5]] - 1;
-
-                        if (mem_done) begin
+                        if (~mem_waiting) begin
+                            mem_read_en  <= 1;
+                            mem_addr     <= pc + regbank[ir[7:5]] - 1;
+                            mem_waiting  <= 1;
+                        end else begin
                             decoded_tmp <= mem_data_out;
                             mem_read_en <= 0;
                             phase       <= `PH_EXECUTE;
+                            mem_waiting <= 0;
                         end
                     end
                 end
@@ -393,23 +414,27 @@ module cu(
                         phase       <= `PH_EXECUTE;
                     end
                     else if (ir[11] == 1 && ir[10] == 0) begin // addressing mode: absolute, indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= {8'd0, ir[7:0]};
-
-                        if (mem_done) begin
+                        if (~mem_waiting) begin
+                            mem_read_en  <= 1;
+                            mem_addr     <= {8'd0, ir[7:0]};
+                            mem_waiting  <= 1;
+                        end else begin
                             decoded_tmp <= mem_data_out;
                             mem_read_en <= 0;
                             phase       <= `PH_EXECUTE;
+                            mem_waiting <= 0;
                         end
                     end
                     else if (ir[11] == 0 && ir[10] == 0) begin // addressing mode: pc relative, indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= pc + {{8{ir[7]}}, ir[7:0]} - 1;
-
-                        if (mem_done) begin
+                        if (~mem_waiting) begin
+                            mem_read_en  <= 1;
+                            mem_addr     <= pc + {{8{ir[7]}}, ir[7:0]} - 1;
+                            mem_waiting  <= 1;
+                        end else begin
                             decoded_tmp <= mem_data_out;
                             mem_read_en <= 0;
                             phase       <= `PH_EXECUTE;
+                            mem_waiting <= 0;
                         end
                     end
                 end
@@ -442,23 +467,27 @@ module cu(
                     phase <= `PH_FETCH;
                 end
                 `OP_LDR: begin
-                    mem_read_en  <= 1;
-                    mem_addr     <= decoded_tmp;
-
-                    if (mem_done) begin
+                    if (~mem_waiting) begin
+                        mem_read_en  <= 1;
+                        mem_addr     <= decoded_tmp;
+                        mem_waiting  <= 1;
+                    end else begin
                         regbank[ir[11:9]] <= mem_data_out; // dereference address
                         mem_read_en       <= 0;
                         phase             <= `PH_FETCH;
+                        mem_waiting       <= 0;
                     end
                 end
                 `OP_STR: begin
-                    mem_write_en  <= 1;
-                    mem_addr      <= decoded_tmp;
-                    mem_data_in   <= regbank[ir[5:3]];
-
-                    if (mem_done) begin
+                    if (~mem_waiting) begin
+                        mem_write_en  <= 1;
+                        mem_addr      <= decoded_tmp;
+                        mem_data_in   <= regbank[ir[5:3]];
+                        mem_waiting   <= 1;
+                    end else begin
                         mem_write_en <= 0;
                         phase        <= `PH_FETCH;
+                        mem_waiting  <= 0;
                     end
                 end
                 `OP_LDI: begin
@@ -472,13 +501,15 @@ module cu(
                         phase <= `PH_FETCH;
                     end
                     else if (ir[0] == 0) begin  // indirect
-                        mem_read_en  <= 1;
-                        mem_addr     <= decoded_tmp;
-
-                        if (mem_done) begin
+                        if (~mem_waiting) begin
+                            mem_read_en  <= 1;
+                            mem_addr     <= decoded_tmp;
+                            mem_waiting  <= 1;
+                        end else begin
                             regbank[ir[11:9]] <= mem_data_out;
                             mem_read_en       <= 0;
                             phase             <= `PH_FETCH;
+                            mem_waiting       <= 0;
                         end
                     end
                 end
diff --git a/atk16_fpga/cu_tb.v b/atk16_fpga/cu_tb.v
index dd7f887..ec23c65 100644
--- a/atk16_fpga/cu_tb.v
+++ b/atk16_fpga/cu_tb.v
@@ -1,6 +1,6 @@
 `default_nettype none
 `define DUMPSTR(x) `"x.vcd`"
-`timescale 10 ns / 100 ps
+`timescale 1 ns / 100 ps
 
 module cu_tb();
 
@@ -30,12 +30,12 @@ module cu_tb();
         #10 // Wait for reset phase to finish
 
         // set up halt instruction at PC = 1, used by all tests
-        dut.bram_fsm_inst.bram_inst.mem[1] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[1] = { 4'b1111, 12'd0 }; // HLT
 
         // test ALR
         dut.regbank[0] = 16'd10;
         dut.regbank[1] = 16'd20;
-        dut.bram_fsm_inst.bram_inst.mem[0] = { 4'b0000, 3'd2, 3'd0, 3'd1, 3'd0 }; // ALR RC, RA, RB, S=PLUS
+        dut.sram_inst.mem[0] = { 4'b0000, 3'd2, 3'd0, 3'd1, 3'd0 }; // ALR RC, RA, RB, S=PLUS
         expected = 16'd30;
 
         #200 if (dut.regbank[2] == expected) begin
@@ -48,7 +48,7 @@ module cu_tb();
 
         // test ALI
         dut.regbank[0] = 16'd10;
-        dut.bram_fsm_inst.bram_inst.mem[0] = { 4'b0001, 3'd2, 3'd0, 3'd7, 3'd0 }; // ALI RC, RA, 7, S=PLUS
+        dut.sram_inst.mem[0] = { 4'b0001, 3'd2, 3'd0, 3'd7, 3'd0 }; // ALI RC, RA, 7, S=PLUS
         expected = 16'd17;
 
         #200 if (dut.regbank[2] == expected) begin
@@ -60,9 +60,9 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDR, absolute addressing
-        dut.bram_fsm_inst.bram_inst.mem[16'd100] = 16'hffff;
+        dut.sram_inst.mem[16'd100] = 16'hffff;
         dut.regbank[1] = 16'd100;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // LDR RA, RB, absolute, direct
+        dut.sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // LDR RA, RB, absolute, direct
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -74,9 +74,9 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDR, relative addressing
-        dut.bram_fsm_inst.bram_inst.mem[16'd10] = 16'hffff;
+        dut.sram_inst.mem[16'd10] = 16'hffff;
         dut.regbank[1] = 16'd10;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // LDR RA, RB, relative, direct
+        dut.sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // LDR RA, RB, relative, direct
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -88,10 +88,10 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDR, absolute addressing, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd100] = 16'd200;
-        dut.bram_fsm_inst.bram_inst.mem[16'd200] = 16'hffff;
+        dut.sram_inst.mem[16'd100] = 16'd200;
+        dut.sram_inst.mem[16'd200] = 16'hffff;
         dut.regbank[1] = 16'd100;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // LDR RA, RB, absolute, indirect
+        dut.sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // LDR RA, RB, absolute, indirect
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -103,10 +103,10 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDR, relative addressing, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd10] = 16'd20;
-        dut.bram_fsm_inst.bram_inst.mem[16'd20] = 16'hffff;
+        dut.sram_inst.mem[16'd10] = 16'd20;
+        dut.sram_inst.mem[16'd20] = 16'hffff;
         dut.regbank[1] = 16'd10;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // LDR RA, RB, relative, indirect
+        dut.sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // LDR RA, RB, relative, indirect
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -120,13 +120,13 @@ module cu_tb();
         // test STR, absolute addressing, direct
         dut.regbank[0] = 16'hfafa;
         dut.regbank[1] = 16'd100;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // STR RB, RA, absolute, direct
+        dut.sram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // STR RB, RA, absolute, direct
         expected = 16'hfafa;
 
-        #200 if (dut.bram_fsm_inst.bram_inst.mem[16'd100] == expected) begin
+        #200 if (dut.sram_inst.mem[16'd100] == expected) begin
             $display("\033[0;32m[PASS]\033[0m STR direct absolute ok");
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR direct absolute not working, memory location contains %04h, expected %04h", dut.bram_fsm_inst.bram_inst.mem[16'd100], expected);
+            $display("\033[0;31m[FAIL]\033[0m STR direct absolute not working, memory location contains %04h, expected %04h", dut.sram_inst.mem[16'd100], expected);
             failed = 1;
         end
         rst = 1; #10 rst = 0; #10
@@ -134,13 +134,13 @@ module cu_tb();
         // test STR, relative addressing, direct
         dut.regbank[0] = 16'hafaf;
         dut.regbank[1] = 16'd10;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // STR RB, RA, relative, direct
+        dut.sram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // STR RB, RA, relative, direct
         expected = 16'hafaf;
 
-        #200 if (dut.bram_fsm_inst.bram_inst.mem[16'd10] == expected) begin
+        #200 if (dut.sram_inst.mem[16'd10] == expected) begin
             $display("\033[0;32m[PASS]\033[0m STR direct relative ok");
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR direct relative not working, memory location contains %04h, expected %04h", dut.bram_fsm_inst.bram_inst.mem[16'd10], expected);
+            $display("\033[0;31m[FAIL]\033[0m STR direct relative not working, memory location contains %04h, expected %04h", dut.sram_inst.mem[16'd10], expected);
             failed = 1;
         end
         rst = 1; #10 rst = 0; #10
@@ -148,14 +148,14 @@ module cu_tb();
         // test STR, absolute addressing, indirect
         dut.regbank[0] = 16'hfafa;
         dut.regbank[1] = 16'd100;
-        dut.bram_fsm_inst.bram_inst.mem[16'd100] = 16'd200;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // STR RB, RA, absolute, indirect
+        dut.sram_inst.mem[16'd100] = 16'd200;
+        dut.sram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // STR RB, RA, absolute, indirect
         expected = 16'hfafa;
 
-        #200 if (dut.bram_fsm_inst.bram_inst.mem[16'd200] == expected) begin
+        #200 if (dut.sram_inst.mem[16'd200] == expected) begin
             $display("\033[0;32m[PASS]\033[0m STR indirect absolute ok");
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR indirect absolute not working, memory location contains %04h, expected %04h", dut.bram_fsm_inst.bram_inst.mem[16'd200], expected);
+            $display("\033[0;31m[FAIL]\033[0m STR indirect absolute not working, memory location contains %04h, expected %04h", dut.sram_inst.mem[16'd200], expected);
             failed = 1;
         end
         rst = 1; #10 rst = 0; #10
@@ -163,21 +163,21 @@ module cu_tb();
         // test STR, relative addressing, indirect
         dut.regbank[0] = 16'hafaf;
         dut.regbank[1] = -16'd10;
-        dut.bram_fsm_inst.bram_inst.mem[16'd10] = 16'd20;
-        dut.bram_fsm_inst.bram_inst.mem[16'd20] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // STR RB, RA, relative, indirect
+        dut.sram_inst.mem[16'd10] = 16'd20;
+        dut.sram_inst.mem[16'd20] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // STR RB, RA, relative, indirect
         dut.pc = 16'd20;
         expected = 16'hafaf;
 
-        #200 if (dut.bram_fsm_inst.bram_inst.mem[16'd20] == expected) begin
+        #200 if (dut.sram_inst.mem[16'd20] == expected) begin
             $display("\033[0;32m[PASS]\033[0m STR indirect relative ok");
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR indirect relative not working, memory location contains %04h, expected %04h", dut.bram_fsm_inst.bram_inst.mem[16'd20], expected);
+            $display("\033[0;31m[FAIL]\033[0m STR indirect relative not working, memory location contains %04h, expected %04h", dut.sram_inst.mem[16'd20], expected);
             failed = 1;
         end
         rst = 1; #10 rst = 0; #10
 
         // test LDI, absolute addressing, direct
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd123, 1'd1, 1'd1 }; // LDI RA, 1, absolute, direct
+        dut.sram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd123, 1'd1, 1'd1 }; // LDI RA, 1, absolute, direct
         expected = 16'd123;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -189,7 +189,7 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDI, relative addressing, direct
-        dut.bram_fsm_inst.bram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd1 }; // LDI RA, 1, relative, direct
+        dut.sram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd1 }; // LDI RA, 1, relative, direct
         dut.pc = 16'd150;
         expected = 16'd130;
 
@@ -202,8 +202,8 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDI, absolute addressing, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd50, 1'd1, 1'd0 }; // LDI RA, 1, absolute, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd50] = 16'd123;
+        dut.sram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd50, 1'd1, 1'd0 }; // LDI RA, 1, absolute, indirect
+        dut.sram_inst.mem[16'd50] = 16'd123;
         expected = 16'd123;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -215,8 +215,8 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDI, relative addressing, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd0 }; // LDI RA, 1, relative, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd130] = 16'd123;
+        dut.sram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd0 }; // LDI RA, 1, relative, indirect
+        dut.sram_inst.mem[16'd130] = 16'd123;
         dut.pc = 16'd150;
         expected = 16'd123;
 
@@ -230,8 +230,8 @@ module cu_tb();
 
         // test JPR, absolute addressing, direct
         dut.regbank[0] = 16'd100;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd1, 3'd0, 7'd0 }; // JPR RA, absolute, direct
-        dut.bram_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd1, 3'd0, 7'd0 }; // JPR RA, absolute, direct
+        dut.sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd101; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -244,8 +244,8 @@ module cu_tb();
 
         // test JPR, relative addressing, direct
         dut.regbank[0] = 16'd50;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0101, 1'd0, 1'd1, 3'd0, 7'd0 }; // JPR RA, relative, direct
-        dut.bram_fsm_inst.bram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd0] = { 4'b0101, 1'd0, 1'd1, 3'd0, 7'd0 }; // JPR RA, relative, direct
+        dut.sram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd51; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -258,9 +258,9 @@ module cu_tb();
 
         // test JPR, absolute addressing, indirect
         dut.regbank[0] = 16'd100;
-        dut.bram_fsm_inst.bram_inst.mem[16'd100] = 16'd200;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd0, 3'd0, 7'd0 }; // JPR RA, absolute, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd100] = 16'd200;
+        dut.sram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd0, 3'd0, 7'd0 }; // JPR RA, absolute, indirect
+        dut.sram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd201; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -273,9 +273,9 @@ module cu_tb();
 
         // test JPR, relative addressing, indirect
         dut.regbank[0] = 16'd50;
-        dut.bram_fsm_inst.bram_inst.mem[16'd60] = 16'd100;
-        dut.bram_fsm_inst.bram_inst.mem[16'd10] = { 4'b0101, 1'd0, 1'd0, 3'd0, 7'd0 }; // JPR RA, relative, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd60] = 16'd100;
+        dut.sram_inst.mem[16'd10] = { 4'b0101, 1'd0, 1'd0, 3'd0, 7'd0 }; // JPR RA, relative, indirect
+        dut.sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
         dut.pc = 16'd10;
         expected = 16'd101; // PC ends up at &HLT + 1
 
@@ -288,8 +288,8 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test JPI, absolute addressing, direct
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0110, 1'd1, 1'd1, 10'd123 }; // JPI 123, absolute, direct
-        dut.bram_fsm_inst.bram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd0] = { 4'b0110, 1'd1, 1'd1, 10'd123 }; // JPI 123, absolute, direct
+        dut.sram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd124; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -301,8 +301,8 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test JPI, relative addressing, direct
-        dut.bram_fsm_inst.bram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd1, -10'd20 }; // JPI -20, relative, direct
-        dut.bram_fsm_inst.bram_inst.mem[16'd10] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd1, -10'd20 }; // JPI -20, relative, direct
+        dut.sram_inst.mem[16'd10] = { 4'b1111, 12'd0 }; // HLT
         dut.pc = 16'd30;
         expected = 16'd11; // PC ends up at &HLT + 1
 
@@ -315,9 +315,9 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test JPI, absolute addressing, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd10] = { 4'b0110, 1'd1, 1'd0, 10'd50 }; // JPI 50, absolute, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd50] = 16'd123;
-        dut.bram_fsm_inst.bram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd10] = { 4'b0110, 1'd1, 1'd0, 10'd50 }; // JPI 50, absolute, indirect
+        dut.sram_inst.mem[16'd50] = 16'd123;
+        dut.sram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT
         dut.pc = 16'd10;
         expected = 16'd124; // PC ends up at &HLT + 1
 
@@ -330,9 +330,9 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test JPI, relative addressing, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd0, -10'd20 }; // JPI -20, relative, indirect
-        dut.bram_fsm_inst.bram_inst.mem[16'd10] = 16'd50;
-        dut.bram_fsm_inst.bram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd0, -10'd20 }; // JPI -20, relative, indirect
+        dut.sram_inst.mem[16'd10] = 16'd50;
+        dut.sram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT
         dut.pc = 16'd30;
         expected = 16'd51; // PC ends up at &HLT + 1
 
@@ -347,10 +347,10 @@ module cu_tb();
         // test BRR, absolute addressing, direct, true branch
         dut.regbank[0] = 16'd100;
         dut.regbank[2] = 16'd110;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.bram_fsm_inst.bram_inst.mem[16'd1]   = { 4'b0111, 1'd1, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=ZERO
-        dut.bram_fsm_inst.bram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
-        dut.bram_fsm_inst.bram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        dut.sram_inst.mem[16'd1]   = { 4'b0111, 1'd1, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=ZERO
+        dut.sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd111; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -364,10 +364,10 @@ module cu_tb();
         // test BRR, absolute addressing, direct, false branch
         dut.regbank[0] = 16'd100;
         dut.regbank[2] = 16'd110;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.bram_fsm_inst.bram_inst.mem[16'd1] = { 4'b0111, 1'd1, 1'd1, 2'd1, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=NEGATIVE
-        dut.bram_fsm_inst.bram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT
-        dut.bram_fsm_inst.bram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        dut.sram_inst.mem[16'd1] = { 4'b0111, 1'd1, 1'd1, 2'd1, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=NEGATIVE
+        dut.sram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd3; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -382,10 +382,10 @@ module cu_tb();
         dut.regbank[0] = 16'd100;
         dut.regbank[2] = 16'd109;
         dut.pc = 16'd10;
-        dut.bram_fsm_inst.bram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.bram_fsm_inst.bram_inst.mem[16'd11]  = { 4'b0111, 1'd0, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, direct, F=ZERO
-        dut.bram_fsm_inst.bram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
-        dut.bram_fsm_inst.bram_inst.mem[16'd120] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        dut.sram_inst.mem[16'd11]  = { 4'b0111, 1'd0, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, direct, F=ZERO
+        dut.sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd120] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd121; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -399,11 +399,11 @@ module cu_tb();
         // test BRR, absolute addressing, indirect
         dut.regbank[0] = 16'd100;
         dut.regbank[2] = 16'd110;
-        dut.bram_fsm_inst.bram_inst.mem[16'd110] = 16'd200;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.bram_fsm_inst.bram_inst.mem[16'd1]   = { 4'b0111, 1'd1, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, indirect, F=ZERO
-        dut.bram_fsm_inst.bram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
-        dut.bram_fsm_inst.bram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd110] = 16'd200;
+        dut.sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        dut.sram_inst.mem[16'd1]   = { 4'b0111, 1'd1, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, indirect, F=ZERO
+        dut.sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd201; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -418,11 +418,11 @@ module cu_tb();
         dut.regbank[0] = 16'd100;
         dut.regbank[2] = 16'd109;
         dut.pc = 16'd10;
-        dut.bram_fsm_inst.bram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.bram_fsm_inst.bram_inst.mem[16'd11]  = { 4'b0111, 1'd0, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, indirect, F=ZERO
-        dut.bram_fsm_inst.bram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
-        dut.bram_fsm_inst.bram_inst.mem[16'd120] = 16'd130;
-        dut.bram_fsm_inst.bram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        dut.sram_inst.mem[16'd11]  = { 4'b0111, 1'd0, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, indirect, F=ZERO
+        dut.sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd120] = 16'd130;
+        dut.sram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd131; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -435,10 +435,10 @@ module cu_tb();
 
         // test BRI, absolute addressing, direct, true branch
         dut.regbank[0] = 16'd100;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.bram_fsm_inst.bram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd1, 2'd0, 8'd100 }; // BRI 100, absolute, direct, F=ZERO
-        dut.bram_fsm_inst.bram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
-        dut.bram_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        dut.sram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd1, 2'd0, 8'd100 }; // BRI 100, absolute, direct, F=ZERO
+        dut.sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd101; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -451,10 +451,10 @@ module cu_tb();
 
         // test BRI, absolute addressing, direct, false branch
         dut.regbank[0] = 16'd100;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.bram_fsm_inst.bram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd1, 2'd1, 8'd100 }; // BRI 100, absolute, direct, F=NEGATIVE
-        dut.bram_fsm_inst.bram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
-        dut.bram_fsm_inst.bram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        dut.sram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd1, 2'd1, 8'd100 }; // BRI 100, absolute, direct, F=NEGATIVE
+        dut.sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd3; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -468,10 +468,10 @@ module cu_tb();
         // test BRI, relative addressing, direct
         dut.regbank[0] = 16'd100;
         dut.pc = 16'd10;
-        dut.bram_fsm_inst.bram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.bram_fsm_inst.bram_inst.mem[16'd11]  = { 4'b1000, 1'd0, 1'd1, 2'd0, 8'd9 }; // BRI 9, relative, direct, F=ZERO
-        dut.bram_fsm_inst.bram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
-        dut.bram_fsm_inst.bram_inst.mem[16'd20]  = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        dut.sram_inst.mem[16'd11]  = { 4'b1000, 1'd0, 1'd1, 2'd0, 8'd9 }; // BRI 9, relative, direct, F=ZERO
+        dut.sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd20]  = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd21; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -484,11 +484,11 @@ module cu_tb();
 
         // test BRI, absolute addressing, indirect
         dut.regbank[0] = 16'd100;
-        dut.bram_fsm_inst.bram_inst.mem[16'd100] = 16'd200;
-        dut.bram_fsm_inst.bram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.bram_fsm_inst.bram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd0, 2'd0, 8'd100 }; // BRI 100, absolute, indirect, F=ZERO
-        dut.bram_fsm_inst.bram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
-        dut.bram_fsm_inst.bram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd100] = 16'd200;
+        dut.sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        dut.sram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd0, 2'd0, 8'd100 }; // BRI 100, absolute, indirect, F=ZERO
+        dut.sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd201; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -502,11 +502,11 @@ module cu_tb();
         // test BRI, relative addressing, indirect
         dut.regbank[0] = 16'd100;
         dut.pc = 16'd10;
-        dut.bram_fsm_inst.bram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.bram_fsm_inst.bram_inst.mem[16'd11]  = { 4'b1000, 1'd0, 1'd0, 2'd0, 8'd9 }; // BRI 9, relative, indirect, F=ZERO
-        dut.bram_fsm_inst.bram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
-        dut.bram_fsm_inst.bram_inst.mem[16'd20]  = 16'd130;
-        dut.bram_fsm_inst.bram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        dut.sram_inst.mem[16'd11]  = { 4'b1000, 1'd0, 1'd0, 2'd0, 8'd9 }; // BRI 9, relative, indirect, F=ZERO
+        dut.sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
+        dut.sram_inst.mem[16'd20]  = 16'd130;
+        dut.sram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd131; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
diff --git a/atk16_fpga/sram.v b/atk16_fpga/sram.v
index c1ccb86..9942bb3 100644
--- a/atk16_fpga/sram.v
+++ b/atk16_fpga/sram.v
@@ -40,11 +40,11 @@ module sram(
     end
 
     always @(*) begin
-        if (addr != last_addr ||
-            data_in != last_data_in ||
-            wr_n != last_wr_n ||
-            rd_n != last_rd_n ||
-            cs_n != last_cs_n
+        if (addr !== last_addr ||
+            data_in !== last_data_in ||
+            wr_n !== last_wr_n ||
+            rd_n !== last_rd_n ||
+            cs_n !== last_cs_n
         ) begin
             //$display("SRAM: addr=%h data_in=%h", addr, data_in);
             last_addr = addr;