Add @let directive, start pondering interrupt control

1 files changed, 5 insertions, 8 deletions

diff --git a/src/asm_pass4.py b/src/asm_pass4.py
index dc65b65..462707a 100644
--- a/src/asm_pass4.py
+++ b/src/asm_pass4.py
@@ -17,7 +17,7 @@ class Result4:
   lines: list[Result4Line]
   options: Options
   operations: OpExpansionDict
-  labels: dict[str, int]
+  symbols: dict[str, int]
 
 def translate_opt(arg: str, options: Options) -> str:
   match arg:
@@ -27,12 +27,11 @@ def translate_opt(arg: str, options: Options) -> str:
 
 def pass_4(result3: Result3) -> Result4:
   result_lines: list[Result4Line] = []
-  address = 0
 
   for line in result3.lines:
     keyword, *args = line.parts
     meta = Meta(
-      address=address,
+      address=line.address,
     )
 
     args = list(map(lambda a: translate_opt(a, result3.options), args))
@@ -41,7 +40,7 @@ def pass_4(result3: Result3) -> Result4:
 
     if keyword in operations:
       fn = operations[keyword]
-      word = fn(meta, result3.labels, *args)
+      word = fn(meta, result3.symbols, *args)
       result_lines.append(Result4Line(
         line_num=line.line_num,
         src_file=line.src_file,
@@ -56,18 +55,16 @@ def pass_4(result3: Result3) -> Result4:
           line_num=line.line_num,
           src_file=line.src_file,
           address=line.address,
-          word=eval_expr(result3.labels, keyword),
+          word=eval_expr(result3.symbols, keyword),
           text=text,
           original_text=original_text,
         ))
       except:
         raise Exception(f"Invalid assembly at {line.src_file}:{line.line_num + 1}\n\n{line}")
 
-    address += 1
-
   return Result4(
     operations=result3.operations,
-    labels=result3.labels,
+    symbols=result3.symbols,
     options=result3.options,
     lines=result_lines,
   )