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authorJan Tuomi <jans.tuomi@gmail.com>2023-04-11 17:30:08 +0300
committerJan Tuomi <jans.tuomi@gmail.com>2023-04-11 18:41:56 +0300
commita38b64e1a1bf14dd9c42629f219b0e422aebe52a (patch)
tree8cc08f712ddd3f8573d2b7c8aa243fcd1b6e52df /src
parente240ef3e9a2854cfe390b47fb0b3d519c095193b (diff)
Add hover and go to definition to extension
Diffstat (limited to 'src')
-rw-r--r--src/asm_pass0.py48
-rw-r--r--src/asm_pass1.py13
-rw-r--r--src/asm_pass2.py2
-rw-r--r--src/asm_pass3.py2
-rw-r--r--src/asm_pass4.py5
-rwxr-xr-xsrc/assembler.py4
-rw-r--r--src/ext_std.py97
7 files changed, 66 insertions, 105 deletions
diff --git a/src/asm_pass0.py b/src/asm_pass0.py
new file mode 100644
index 0000000..be6c46a
--- /dev/null
+++ b/src/asm_pass0.py
@@ -0,0 +1,48 @@
+from dataclasses import dataclass
+from asm_ops import *
+from asm_eval import *
+
+@dataclass
+class Result0Line:
+ line_num: int
+ src_file: str
+ line: str
+
+@dataclass
+class Result0:
+ lines: list[Result0Line]
+ options: Options
+ operations: OpExpansionDict
+
+def pass_0(lines: list[str], file_name: str) -> Result0:
+ options = Options()
+ result_lines: list[Result0Line] = []
+ operations: OpExpansionDict = default_expansions.copy()
+
+ for (line_num, line) in enumerate(lines):
+ line = line.split(";")[0].strip()
+ if line == "": continue
+ keyword, *args = line.lower().split()
+ match keyword:
+ case "@include":
+ asm_file_name = args[0]
+ with open(asm_file_name, "r") as f:
+ for incl_line in f.readlines():
+ result_lines.append(Result0Line(
+ src_file=asm_file_name,
+ line_num=line_num,
+ line=incl_line
+ ))
+
+ case _:
+ result_lines.append(Result0Line(
+ src_file=file_name,
+ line_num=line_num,
+ line=line
+ ))
+
+ return Result0(
+ operations=operations,
+ options=options,
+ lines=result_lines
+ )
diff --git a/src/asm_pass1.py b/src/asm_pass1.py
index 606a1a1..fee72ff 100644
--- a/src/asm_pass1.py
+++ b/src/asm_pass1.py
@@ -2,10 +2,12 @@ import importlib
from dataclasses import dataclass
from asm_ops import *
from asm_eval import *
+from asm_pass0 import *
@dataclass
class Result1Line:
line_num: int
+ src_file: str
parts: list[str]
@dataclass
@@ -14,15 +16,13 @@ class Result1:
options: Options
operations: OpExpansionDict
-def pass_1(lines: list[str]) -> Result1:
+def pass_1(result0: Result0) -> Result1:
options = Options()
result_lines: list[Result1Line] = []
operations: OpExpansionDict = default_expansions.copy()
- for (line_num, line) in enumerate(lines):
- line = line.split(";")[0].strip()
- if line == "": continue
- keyword, *args = line.lower().split()
+ for line in result0.lines:
+ keyword, *args = line.line.lower().split()
match keyword:
case "@opt":
opt_name, opt_value = args
@@ -41,7 +41,8 @@ def pass_1(lines: list[str]) -> Result1:
operations[op] = expansion
case _:
result_lines.append(Result1Line(
- line_num=line_num,
+ src_file=line.src_file,
+ line_num=line.line_num,
parts=[keyword, *args]
))
diff --git a/src/asm_pass2.py b/src/asm_pass2.py
index e7f48ac..7272dcf 100644
--- a/src/asm_pass2.py
+++ b/src/asm_pass2.py
@@ -6,6 +6,7 @@ from asm_pass1 import *
@dataclass
class Result2Line:
line_num: int
+ src_file: str
parts: list[str]
original_parts: list[str]
@@ -30,6 +31,7 @@ def pass_2(result1: Result1) -> Result2:
for (idx, parts) in enumerate(output):
result_lines.append(Result2Line(
line_num=line.line_num,
+ src_file=line.src_file,
parts=parts,
original_parts=line.parts if idx == 0 else ["..."]
))
diff --git a/src/asm_pass3.py b/src/asm_pass3.py
index 038e3f7..76e7b84 100644
--- a/src/asm_pass3.py
+++ b/src/asm_pass3.py
@@ -6,6 +6,7 @@ from asm_pass2 import *
@dataclass
class Result3Line:
line_num: int
+ src_file: str
address: int
parts: list[str]
original_parts: list[str]
@@ -34,6 +35,7 @@ def pass_3(result2: Result2) -> Result3:
case _:
result_lines.append(Result3Line(
line_num=line.line_num,
+ src_file=line.src_file,
parts=line.parts,
address=address,
original_parts=line.original_parts,
diff --git a/src/asm_pass4.py b/src/asm_pass4.py
index 3d4f45c..dc65b65 100644
--- a/src/asm_pass4.py
+++ b/src/asm_pass4.py
@@ -6,6 +6,7 @@ from asm_pass3 import *
@dataclass
class Result4Line:
line_num: int
+ src_file: str
address: int
word: int
text: str
@@ -43,6 +44,7 @@ def pass_4(result3: Result3) -> Result4:
word = fn(meta, result3.labels, *args)
result_lines.append(Result4Line(
line_num=line.line_num,
+ src_file=line.src_file,
address=line.address,
word=word,
text=text,
@@ -52,13 +54,14 @@ def pass_4(result3: Result3) -> Result4:
try:
result_lines.append(Result4Line(
line_num=line.line_num,
+ src_file=line.src_file,
address=line.address,
word=eval_expr(result3.labels, keyword),
text=text,
original_text=original_text,
))
except:
- raise Exception(f"Invalid assembly at {line.line_num + 1}\n\n{line}")
+ raise Exception(f"Invalid assembly at {line.src_file}:{line.line_num + 1}\n\n{line}")
address += 1
diff --git a/src/assembler.py b/src/assembler.py
index 3f0c8bc..8f84288 100755
--- a/src/assembler.py
+++ b/src/assembler.py
@@ -4,6 +4,7 @@
import sys
from asm_ops import *
from asm_eval import *
+from asm_pass0 import pass_0
from asm_pass1 import pass_1
from asm_pass2 import pass_2
from asm_pass3 import pass_3
@@ -49,7 +50,8 @@ def parse(line: str) -> list[str]:
result.append(acc)
return list(filter(lambda x: len(x) > 0, result))
-result1 = pass_1(src_lines)
+result0 = pass_0(src_lines, infile_path)
+result1 = pass_1(result0)
result2 = pass_2(result1)
result3 = pass_3(result2)
result4 = pass_4(result3)
diff --git a/src/ext_std.py b/src/ext_std.py
deleted file mode 100644
index 11da8aa..0000000
--- a/src/ext_std.py
+++ /dev/null
@@ -1,97 +0,0 @@
-from asm_ops import *
-
-def expand_add(left: str, right: str, target: str) -> ExpandResult:
- return [["alr", "al_plus", left, right, target]]
-
-def expand_sub(left: str, right: str, target: str) -> ExpandResult:
- return [["alr", "al_minus", left, right, target]]
-
-def expand_addi(left: str, imm: str, target: str) -> ExpandResult:
- return [["ali", "al_plus", left, imm, target]]
-
-def expand_subi(left: str, imm: str, target: str) -> ExpandResult:
- return [["ali", "al_minus", left, imm, target]]
-
-def expand_and(left: str, right: str, target: str) -> ExpandResult:
- return [["alr", "al_and", left, right, target]]
-
-def expand_or(left: str, right: str, target: str) -> ExpandResult:
- return [["alr", "al_or", left, right, target]]
-
-def expand_xor(left: str, right: str, target: str) -> ExpandResult:
- return [["alr", "al_xor", left, right, target]]
-
-def expand_sll(left: str, right: str, target: str) -> ExpandResult:
- return [["alr", "al_sll", left, right, target]]
-
-def expand_slr(left: str, right: str, target: str) -> ExpandResult:
- return [["alr", "al_slr", left, right, target]]
-
-def expand_sar(left: str, right: str, target: str) -> ExpandResult:
- return [["alr", "al_sar", left, right, target]]
-
-def expand_slli(left: str, imm: str, target: str) -> ExpandResult:
- return [["ali", "al_sll", left, imm, target]]
-
-def expand_slri(left: str, imm: str, target: str) -> ExpandResult:
- return [["ali", "al_slr", left, imm, target]]
-
-def expand_sari(left: str, imm: str, target: str) -> ExpandResult:
- return [["ali", "al_sar", left, imm, target]]
-
-def expand_inc(reg: str) -> ExpandResult:
- return [["ali", "al_plus", reg, "1", reg]]
-
-def expand_dec(reg: str) -> ExpandResult:
- return [["ali", "al_minus", reg, "1", reg]]
-
-def expand_mov(from_reg: str, to_reg: str) -> ExpandResult:
- return [["ali", "al_plus", from_reg, "0", to_reg]]
-
-def expand_spu(reg: str) -> ExpandResult:
- return [["str", reg, "__STACK_POINTER"]] + expand_inc("__STACK_POINTER")
-
-def expand_spo(reg: str):
- return expand_dec("__STACK_POINTER") + [["ldr", "__STACK_POINTER", reg]]
-
-def expand_csr(addr_reg: str):
- return [
- ["lpc", "__CSR_SCRATCH"],
- *expand_addi("__CSR_SCRATCH", "4", "__CSR_SCRATCH"),
- *expand_spu("__CSR_SCRATCH"),
- ["jpr", addr_reg]
- ]
-
-def expand_csi(addr_imm: str):
- return [
- ["lpc", "__CSR_SCRATCH"],
- *expand_addi("__CSR_SCRATCH", "4", "__CSR_SCRATCH"),
- *expand_spu("__CSR_SCRATCH"),
- ["jpi", addr_imm]
- ]
-def expand_rsr():
- return expand_spo("__CSR_SCRATCH") + [["jpr", "__CSR_SCRATCH"]]
-
-expansions: OpExpansionDict = {
- "add": expand_add,
- "sub": expand_sub,
- "addi": expand_addi,
- "subi": expand_subi,
- "and": expand_and,
- "or": expand_or,
- "xor": expand_xor,
- "sll": expand_sll,
- "slr": expand_slr,
- "sar": expand_sar,
- "slli": expand_slli,
- "slri": expand_slri,
- "sari": expand_sari,
- "inc": expand_inc,
- "dec": expand_dec,
- "mov": expand_mov,
- "spu": expand_spu,
- "spo": expand_spo,
- "csr": expand_csr,
- "csi": expand_csi,
- "rsr": expand_rsr,
-}