Move sram out of cu module

3 files changed, 260 insertions, 229 deletions

diff --git a/atk16_fpga/cu.v b/atk16_fpga/cu.v
index e68a3d5..1f8ea60 100644
--- a/atk16_fpga/cu.v
+++ b/atk16_fpga/cu.v
@@ -65,7 +65,13 @@
 module cu(
     input wire clk,
     input wire rst,
-    input wire [3:0] int_lines
+    input wire [3:0] int_lines,
+
+    output reg  [15:0] sram_addr,
+    output reg  [15:0] sram_in,
+    input  wire [15:0] sram_out,
+    output wire sram_cs_n,
+    output reg  sram_wr_n, sram_rd_n
 );
     reg  [15:0] regbank [0:7];
     reg  [15:0] decoded_tmp;
@@ -79,19 +85,8 @@ module cu(
     reg [3:0]  int_line_regs;
     reg int_en = 1;
 
-    reg  [15:0] mem_addr;
-    reg  [15:0] mem_data_in;
-    reg  mem_read_en, mem_write_en;
-    wire [15:0] mem_data_out;
-    reg  mem_waiting = 0;
-    sram sram_inst(
-        .cs_n(1'd0),
-        .wr_n(~mem_write_en),
-        .rd_n(~mem_read_en),
-        .addr({ 2'd0, mem_addr }),
-        .data_in(mem_data_in),
-        .data_out(mem_data_out)
-    );
+    reg  sram_waiting = 0;
+    assign sram_cs_n = 1'b0;
 
     reg  [2:0]  alu_sel;
     reg  [15:0] alu_a;
@@ -124,6 +119,7 @@ module cu(
 
     integer i;
     always @(posedge clk or posedge rst) begin
+
         // Handle reset button
         if (rst) begin
             phase  <= `PH_RESET;
@@ -161,8 +157,8 @@ module cu(
             phase <= `PH_FETCH;
 
             pc <= 16'd0;
-            mem_read_en   <= 0;
-            mem_write_en  <= 0;
+            sram_rd_n     <= 1;
+            sram_wr_n     <= 1;
 
             for (i = 0; i < 8; i = i + 1) begin
                 regbank[i] <= 16'd0;
@@ -171,16 +167,16 @@ module cu(
 
         // Fetch stage
         else if (phase == `PH_FETCH) begin
-            if (~mem_waiting) begin
-                mem_read_en  <= 1;
-                mem_addr     <= pc;
-                mem_waiting  <= 1;
+            if (~sram_waiting) begin
+                sram_rd_n    <= 0;
+                sram_addr    <= pc;
+                sram_waiting <= 1;
             end else begin
-                mem_read_en  <= 0;
-                ir           <= mem_data_out;
+                sram_rd_n    <= 1;
+                ir           <= sram_out;
                 phase        <= `PH_DECODE;
                 pc           <= pc + 16'd1;
-                mem_waiting  <= 0;
+                sram_waiting <= 0;
             end
         end
 
@@ -212,27 +208,27 @@ module cu(
                         phase <= `PH_EXECUTE;
                     end
                     else if (ir[1] == 1 && ir[0] == 0) begin  // addressing mode: absolute, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en    <= 1;
-                            mem_addr       <= regbank[ir[8:6]];
-                            mem_waiting    <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n      <= 0;
+                            sram_addr      <= regbank[ir[8:6]];
+                            sram_waiting   <= 1;
                         end else begin
-                            decoded_tmp    <= mem_data_out;
-                            mem_read_en    <= 0;
+                            decoded_tmp    <= sram_out;
+                            sram_rd_n      <= 1;
                             phase          <= `PH_EXECUTE;
-                            mem_waiting    <= 0;
+                            sram_waiting   <= 0;
                         end
                     end
                     else if (ir[1] == 0 && ir[0] == 0) begin // addressing mode: pc relative, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en    <= 1;
-                            mem_addr       <= pc + regbank[ir[8:6]] - 1;
-                            mem_waiting    <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n      <= 0;
+                            sram_addr      <= pc + regbank[ir[8:6]] - 1;
+                            sram_waiting   <= 1;
                         end else begin
-                            decoded_tmp    <= mem_data_out;
-                            mem_read_en    <= 0;
+                            decoded_tmp    <= sram_out;
+                            sram_rd_n      <= 1;
                             phase          <= `PH_EXECUTE;
-                            mem_waiting    <= 0;
+                            sram_waiting   <= 0;
                         end
                     end
                 end
@@ -251,27 +247,27 @@ module cu(
                         phase <= `PH_EXECUTE;
                     end
                     else if (ir[1] == 1 && ir[0] == 0) begin  // addressing mode: absolute, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en    <= 1;
-                            mem_addr       <= regbank[ir[8:6]];
-                            mem_waiting    <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n      <= 0;
+                            sram_addr      <= regbank[ir[8:6]];
+                            sram_waiting   <= 1;
                         end else begin
-                            decoded_tmp    <= mem_data_out;
-                            mem_read_en    <= 0;
+                            decoded_tmp    <= sram_out;
+                            sram_rd_n      <= 1;
                             phase          <= `PH_EXECUTE;
-                            mem_waiting    <= 0;
+                            sram_waiting   <= 0;
                         end
                     end
                     else if (ir[1] == 0 && ir[0] == 0) begin // addressing mode: pc relative, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en    <= 1;
-                            mem_addr       <= pc + regbank[ir[8:6]] - 1;
-                            mem_waiting    <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n      <= 0;
+                            sram_addr      <= pc + regbank[ir[8:6]] - 1;
+                            sram_waiting   <= 1;
                         end else begin
-                            decoded_tmp    <= mem_data_out;
-                            mem_read_en    <= 0;
+                            decoded_tmp    <= sram_out;
+                            sram_rd_n      <= 1;
                             phase          <= `PH_EXECUTE;
-                            mem_waiting    <= 0;
+                            sram_waiting   <= 0;
                         end
                     end
                 end
@@ -301,27 +297,27 @@ module cu(
                         phase       <= `PH_FETCH;
                     end
                     else if (ir[11] == 1 && ir[10] == 0) begin // addressing mode: absolute, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en  <= 1;
-                            mem_addr     <= regbank[ir[9:6]];
-                            mem_waiting  <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n    <= 0;
+                            sram_addr    <= regbank[ir[9:6]];
+                            sram_waiting <= 1;
                         end else begin
-                            pc          <= mem_data_out;
-                            mem_read_en <= 0;
+                            pc          <= sram_out;
+                            sram_rd_n   <= 1;
                             phase       <= `PH_FETCH;
-                            mem_waiting <= 0;
+                            sram_waiting <= 0;
                         end
                     end
                     else if (ir[11] == 0 && ir[10] == 0) begin // addressing mode: pc relative, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en  <= 1;
-                            mem_addr     <= pc + regbank[ir[9:6]] - 1;
-                            mem_waiting  <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n    <= 0;
+                            sram_addr    <= pc + regbank[ir[9:6]] - 1;
+                            sram_waiting <= 1;
                         end else begin
-                            pc          <= mem_data_out;
-                            mem_read_en <= 0;
+                            pc          <= sram_out;
+                            sram_rd_n   <= 1;
                             phase       <= `PH_FETCH;
-                            mem_waiting <= 0;
+                            sram_waiting <= 0;
                         end
                     end
                 end
@@ -338,27 +334,27 @@ module cu(
                         phase       <= `PH_FETCH;
                     end
                     else if (ir[11] == 1 && ir[10] == 0) begin // addressing mode: absolute, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en  <= 1;
-                            mem_addr     <= {6'd0, ir[9:0]};
-                            mem_waiting  <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n    <= 0;
+                            sram_addr    <= {6'd0, ir[9:0]};
+                            sram_waiting <= 1;
                         end else begin
-                            pc          <= mem_data_out;
-                            mem_read_en <= 0;
+                            pc          <= sram_out;
+                            sram_rd_n   <= 1;
                             phase       <= `PH_FETCH;
-                            mem_waiting <= 0;
+                            sram_waiting <= 0;
                         end
                     end
                     else if (ir[11] == 0 && ir[10] == 0) begin // addressing mode: pc relative, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en  <= 1;
-                            mem_addr     <= pc + {{6{ir[9]}}, ir[9:0]} - 1;
-                            mem_waiting  <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n    <= 0;
+                            sram_addr    <= pc + {{6{ir[9]}}, ir[9:0]} - 1;
+                            sram_waiting <= 1;
                         end else begin
-                            pc          <= mem_data_out;
-                            mem_read_en <= 0;
+                            pc          <= sram_out;
+                            sram_rd_n   <= 1;
                             phase       <= `PH_FETCH;
-                            mem_waiting <= 0;
+                            sram_waiting <= 0;
                         end
                     end
                 end
@@ -376,27 +372,27 @@ module cu(
                         phase       <= `PH_EXECUTE;
                     end
                     else if (ir[11] == 1 && ir[10] == 0) begin // addressing mode: absolute, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en  <= 1;
-                            mem_addr     <= regbank[ir[7:5]];
-                            mem_waiting  <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n    <= 0;
+                            sram_addr    <= regbank[ir[7:5]];
+                            sram_waiting <= 1;
                         end else begin
-                            decoded_tmp <= mem_data_out;
-                            mem_read_en <= 0;
+                            decoded_tmp <= sram_out;
+                            sram_rd_n   <= 1;
                             phase       <= `PH_EXECUTE;
-                            mem_waiting <= 0;
+                            sram_waiting <= 0;
                         end
                     end
                     else if (ir[11] == 0 && ir[10] == 0) begin // addressing mode: pc relative, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en  <= 1;
-                            mem_addr     <= pc + regbank[ir[7:5]] - 1;
-                            mem_waiting  <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n    <= 0;
+                            sram_addr    <= pc + regbank[ir[7:5]] - 1;
+                            sram_waiting <= 1;
                         end else begin
-                            decoded_tmp <= mem_data_out;
-                            mem_read_en <= 0;
+                            decoded_tmp <= sram_out;
+                            sram_rd_n   <= 1;
                             phase       <= `PH_EXECUTE;
-                            mem_waiting <= 0;
+                            sram_waiting <= 0;
                         end
                     end
                 end
@@ -414,27 +410,27 @@ module cu(
                         phase       <= `PH_EXECUTE;
                     end
                     else if (ir[11] == 1 && ir[10] == 0) begin // addressing mode: absolute, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en  <= 1;
-                            mem_addr     <= {8'd0, ir[7:0]};
-                            mem_waiting  <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n    <= 0;
+                            sram_addr    <= {8'd0, ir[7:0]};
+                            sram_waiting <= 1;
                         end else begin
-                            decoded_tmp <= mem_data_out;
-                            mem_read_en <= 0;
+                            decoded_tmp <= sram_out;
+                            sram_rd_n   <= 1;
                             phase       <= `PH_EXECUTE;
-                            mem_waiting <= 0;
+                            sram_waiting <= 0;
                         end
                     end
                     else if (ir[11] == 0 && ir[10] == 0) begin // addressing mode: pc relative, indirect
-                        if (~mem_waiting) begin
-                            mem_read_en  <= 1;
-                            mem_addr     <= pc + {{8{ir[7]}}, ir[7:0]} - 1;
-                            mem_waiting  <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n    <= 0;
+                            sram_addr    <= pc + {{8{ir[7]}}, ir[7:0]} - 1;
+                            sram_waiting <= 1;
                         end else begin
-                            decoded_tmp <= mem_data_out;
-                            mem_read_en <= 0;
+                            decoded_tmp <= sram_out;
+                            sram_rd_n   <= 1;
                             phase       <= `PH_EXECUTE;
-                            mem_waiting <= 0;
+                            sram_waiting <= 0;
                         end
                     end
                 end
@@ -467,27 +463,27 @@ module cu(
                     phase <= `PH_FETCH;
                 end
                 `OP_LDR: begin
-                    if (~mem_waiting) begin
-                        mem_read_en  <= 1;
-                        mem_addr     <= decoded_tmp;
-                        mem_waiting  <= 1;
+                    if (~sram_waiting) begin
+                        sram_rd_n    <= 0;
+                        sram_addr    <= decoded_tmp;
+                        sram_waiting <= 1;
                     end else begin
-                        regbank[ir[11:9]] <= mem_data_out; // dereference address
-                        mem_read_en       <= 0;
+                        regbank[ir[11:9]] <= sram_out; // dereference address
+                        sram_rd_n         <= 1;
                         phase             <= `PH_FETCH;
-                        mem_waiting       <= 0;
+                        sram_waiting      <= 0;
                     end
                 end
                 `OP_STR: begin
-                    if (~mem_waiting) begin
-                        mem_write_en  <= 1;
-                        mem_addr      <= decoded_tmp;
-                        mem_data_in   <= regbank[ir[5:3]];
-                        mem_waiting   <= 1;
+                    if (~sram_waiting) begin
+                        sram_wr_n     <= 0;
+                        sram_addr     <= decoded_tmp;
+                        sram_in       <= regbank[ir[5:3]];
+                        sram_waiting  <= 1;
                     end else begin
-                        mem_write_en <= 0;
+                        sram_wr_n    <= 1;
                         phase        <= `PH_FETCH;
-                        mem_waiting  <= 0;
+                        sram_waiting <= 0;
                     end
                 end
                 `OP_LDI: begin
@@ -501,15 +497,15 @@ module cu(
                         phase <= `PH_FETCH;
                     end
                     else if (ir[0] == 0) begin  // indirect
-                        if (~mem_waiting) begin
-                            mem_read_en  <= 1;
-                            mem_addr     <= decoded_tmp;
-                            mem_waiting  <= 1;
+                        if (~sram_waiting) begin
+                            sram_rd_n    <= 0;
+                            sram_addr    <= decoded_tmp;
+                            sram_waiting <= 1;
                         end else begin
-                            regbank[ir[11:9]] <= mem_data_out;
-                            mem_read_en       <= 0;
+                            regbank[ir[11:9]] <= sram_out;
+                            sram_rd_n         <= 1;
                             phase             <= `PH_FETCH;
-                            mem_waiting       <= 0;
+                            sram_waiting      <= 0;
                         end
                     end
                 end
diff --git a/atk16_fpga/cu_tb.v b/atk16_fpga/cu_tb.v
index ec23c65..8c8ec10 100644
--- a/atk16_fpga/cu_tb.v
+++ b/atk16_fpga/cu_tb.v
@@ -7,10 +7,33 @@ module cu_tb();
     reg clk, rst;
     reg [3:0] int_lines;
 
+    wire sram_cs_n, sram_wr_n, sram_rd_n;
+    wire [17:0] sram_addr;
+    wire [15:0] sram_data_in;
+    wire [15:0] sram_data_out;
+    sram sram_inst(
+        .cs_n(sram_cs_n),
+        .wr_n(sram_wr_n),
+        .rd_n(sram_rd_n),
+        .addr(sram_addr),
+        .data_in(sram_data_in),
+        .data_out(sram_data_out)
+    );
+
+    wire [15:0] sram_addr_short;
+    assign sram_addr = { 2'b0, sram_addr_short };
+
     cu dut(
         .clk(clk),
         .rst(rst),
-        .int_lines(int_lines)
+        .int_lines(int_lines),
+
+        .sram_cs_n(sram_cs_n),
+        .sram_wr_n(sram_wr_n),
+        .sram_rd_n(sram_rd_n),
+        .sram_addr(sram_addr_short),
+        .sram_in(sram_data_in),
+        .sram_out(sram_data_out)
     );
 
     // Clock generation
@@ -30,12 +53,12 @@ module cu_tb();
         #10 // Wait for reset phase to finish
 
         // set up halt instruction at PC = 1, used by all tests
-        dut.sram_inst.mem[1] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[1] = { 4'b1111, 12'd0 }; // HLT
 
         // test ALR
         dut.regbank[0] = 16'd10;
         dut.regbank[1] = 16'd20;
-        dut.sram_inst.mem[0] = { 4'b0000, 3'd2, 3'd0, 3'd1, 3'd0 }; // ALR RC, RA, RB, S=PLUS
+        sram_inst.mem[0] = { 4'b0000, 3'd2, 3'd0, 3'd1, 3'd0 }; // ALR RC, RA, RB, S=PLUS
         expected = 16'd30;
 
         #200 if (dut.regbank[2] == expected) begin
@@ -48,7 +71,7 @@ module cu_tb();
 
         // test ALI
         dut.regbank[0] = 16'd10;
-        dut.sram_inst.mem[0] = { 4'b0001, 3'd2, 3'd0, 3'd7, 3'd0 }; // ALI RC, RA, 7, S=PLUS
+        sram_inst.mem[0] = { 4'b0001, 3'd2, 3'd0, 3'd7, 3'd0 }; // ALI RC, RA, 7, S=PLUS
         expected = 16'd17;
 
         #200 if (dut.regbank[2] == expected) begin
@@ -60,9 +83,9 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDR, absolute addressing
-        dut.sram_inst.mem[16'd100] = 16'hffff;
+        sram_inst.mem[16'd100] = 16'hffff;
         dut.regbank[1] = 16'd100;
-        dut.sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // LDR RA, RB, absolute, direct
+        sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // LDR RA, RB, absolute, direct
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -74,9 +97,9 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDR, relative addressing
-        dut.sram_inst.mem[16'd10] = 16'hffff;
+        sram_inst.mem[16'd10] = 16'hffff;
         dut.regbank[1] = 16'd10;
-        dut.sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // LDR RA, RB, relative, direct
+        sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // LDR RA, RB, relative, direct
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -88,10 +111,10 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDR, absolute addressing, indirect
-        dut.sram_inst.mem[16'd100] = 16'd200;
-        dut.sram_inst.mem[16'd200] = 16'hffff;
+        sram_inst.mem[16'd100] = 16'd200;
+        sram_inst.mem[16'd200] = 16'hffff;
         dut.regbank[1] = 16'd100;
-        dut.sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // LDR RA, RB, absolute, indirect
+        sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // LDR RA, RB, absolute, indirect
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -103,10 +126,10 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDR, relative addressing, indirect
-        dut.sram_inst.mem[16'd10] = 16'd20;
-        dut.sram_inst.mem[16'd20] = 16'hffff;
+        sram_inst.mem[16'd10] = 16'd20;
+        sram_inst.mem[16'd20] = 16'hffff;
         dut.regbank[1] = 16'd10;
-        dut.sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // LDR RA, RB, relative, indirect
+        sram_inst.mem[16'd0] = { 4'b0010, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // LDR RA, RB, relative, indirect
         expected = 16'hffff;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -120,13 +143,13 @@ module cu_tb();
         // test STR, absolute addressing, direct
         dut.regbank[0] = 16'hfafa;
         dut.regbank[1] = 16'd100;
-        dut.sram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // STR RB, RA, absolute, direct
+        sram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd1 }; // STR RB, RA, absolute, direct
         expected = 16'hfafa;
 
-        #200 if (dut.sram_inst.mem[16'd100] == expected) begin
+        #200 if (sram_inst.mem[16'd100] == expected) begin
             $display("\033[0;32m[PASS]\033[0m STR direct absolute ok");
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR direct absolute not working, memory location contains %04h, expected %04h", dut.sram_inst.mem[16'd100], expected);
+            $display("\033[0;31m[FAIL]\033[0m STR direct absolute not working, memory location contains %04h, expected %04h", sram_inst.mem[16'd100], expected);
             failed = 1;
         end
         rst = 1; #10 rst = 0; #10
@@ -134,13 +157,13 @@ module cu_tb();
         // test STR, relative addressing, direct
         dut.regbank[0] = 16'hafaf;
         dut.regbank[1] = 16'd10;
-        dut.sram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // STR RB, RA, relative, direct
+        sram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd1 }; // STR RB, RA, relative, direct
         expected = 16'hafaf;
 
-        #200 if (dut.sram_inst.mem[16'd10] == expected) begin
+        #200 if (sram_inst.mem[16'd10] == expected) begin
             $display("\033[0;32m[PASS]\033[0m STR direct relative ok");
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR direct relative not working, memory location contains %04h, expected %04h", dut.sram_inst.mem[16'd10], expected);
+            $display("\033[0;31m[FAIL]\033[0m STR direct relative not working, memory location contains %04h, expected %04h", sram_inst.mem[16'd10], expected);
             failed = 1;
         end
         rst = 1; #10 rst = 0; #10
@@ -148,14 +171,14 @@ module cu_tb();
         // test STR, absolute addressing, indirect
         dut.regbank[0] = 16'hfafa;
         dut.regbank[1] = 16'd100;
-        dut.sram_inst.mem[16'd100] = 16'd200;
-        dut.sram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // STR RB, RA, absolute, indirect
+        sram_inst.mem[16'd100] = 16'd200;
+        sram_inst.mem[16'd0] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd1, 1'd0 }; // STR RB, RA, absolute, indirect
         expected = 16'hfafa;
 
-        #200 if (dut.sram_inst.mem[16'd200] == expected) begin
+        #200 if (sram_inst.mem[16'd200] == expected) begin
             $display("\033[0;32m[PASS]\033[0m STR indirect absolute ok");
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR indirect absolute not working, memory location contains %04h, expected %04h", dut.sram_inst.mem[16'd200], expected);
+            $display("\033[0;31m[FAIL]\033[0m STR indirect absolute not working, memory location contains %04h, expected %04h", sram_inst.mem[16'd200], expected);
             failed = 1;
         end
         rst = 1; #10 rst = 0; #10
@@ -163,21 +186,21 @@ module cu_tb();
         // test STR, relative addressing, indirect
         dut.regbank[0] = 16'hafaf;
         dut.regbank[1] = -16'd10;
-        dut.sram_inst.mem[16'd10] = 16'd20;
-        dut.sram_inst.mem[16'd20] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // STR RB, RA, relative, indirect
+        sram_inst.mem[16'd10] = 16'd20;
+        sram_inst.mem[16'd20] = { 4'b0011, 3'd0, 3'd1, 4'd0, 1'd0, 1'd0 }; // STR RB, RA, relative, indirect
         dut.pc = 16'd20;
         expected = 16'hafaf;
 
-        #200 if (dut.sram_inst.mem[16'd20] == expected) begin
+        #200 if (sram_inst.mem[16'd20] == expected) begin
             $display("\033[0;32m[PASS]\033[0m STR indirect relative ok");
         end else begin
-            $display("\033[0;31m[FAIL]\033[0m STR indirect relative not working, memory location contains %04h, expected %04h", dut.sram_inst.mem[16'd20], expected);
+            $display("\033[0;31m[FAIL]\033[0m STR indirect relative not working, memory location contains %04h, expected %04h", sram_inst.mem[16'd20], expected);
             failed = 1;
         end
         rst = 1; #10 rst = 0; #10
 
         // test LDI, absolute addressing, direct
-        dut.sram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd123, 1'd1, 1'd1 }; // LDI RA, 1, absolute, direct
+        sram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd123, 1'd1, 1'd1 }; // LDI RA, 1, absolute, direct
         expected = 16'd123;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -189,7 +212,7 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDI, relative addressing, direct
-        dut.sram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd1 }; // LDI RA, 1, relative, direct
+        sram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd1 }; // LDI RA, 1, relative, direct
         dut.pc = 16'd150;
         expected = 16'd130;
 
@@ -202,8 +225,8 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDI, absolute addressing, indirect
-        dut.sram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd50, 1'd1, 1'd0 }; // LDI RA, 1, absolute, indirect
-        dut.sram_inst.mem[16'd50] = 16'd123;
+        sram_inst.mem[16'd0] = { 4'b0100, 3'd0, 7'd50, 1'd1, 1'd0 }; // LDI RA, 1, absolute, indirect
+        sram_inst.mem[16'd50] = 16'd123;
         expected = 16'd123;
 
         #200 if (dut.regbank[0] == expected) begin
@@ -215,8 +238,8 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test LDI, relative addressing, indirect
-        dut.sram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd0 }; // LDI RA, 1, relative, indirect
-        dut.sram_inst.mem[16'd130] = 16'd123;
+        sram_inst.mem[16'd150] = { 4'b0100, 3'd0, -7'd20, 1'd0, 1'd0 }; // LDI RA, 1, relative, indirect
+        sram_inst.mem[16'd130] = 16'd123;
         dut.pc = 16'd150;
         expected = 16'd123;
 
@@ -230,8 +253,8 @@ module cu_tb();
 
         // test JPR, absolute addressing, direct
         dut.regbank[0] = 16'd100;
-        dut.sram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd1, 3'd0, 7'd0 }; // JPR RA, absolute, direct
-        dut.sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd1, 3'd0, 7'd0 }; // JPR RA, absolute, direct
+        sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd101; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -244,8 +267,8 @@ module cu_tb();
 
         // test JPR, relative addressing, direct
         dut.regbank[0] = 16'd50;
-        dut.sram_inst.mem[16'd0] = { 4'b0101, 1'd0, 1'd1, 3'd0, 7'd0 }; // JPR RA, relative, direct
-        dut.sram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd0] = { 4'b0101, 1'd0, 1'd1, 3'd0, 7'd0 }; // JPR RA, relative, direct
+        sram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd51; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -258,9 +281,9 @@ module cu_tb();
 
         // test JPR, absolute addressing, indirect
         dut.regbank[0] = 16'd100;
-        dut.sram_inst.mem[16'd100] = 16'd200;
-        dut.sram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd0, 3'd0, 7'd0 }; // JPR RA, absolute, indirect
-        dut.sram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd100] = 16'd200;
+        sram_inst.mem[16'd0] = { 4'b0101, 1'd1, 1'd0, 3'd0, 7'd0 }; // JPR RA, absolute, indirect
+        sram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd201; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -273,9 +296,9 @@ module cu_tb();
 
         // test JPR, relative addressing, indirect
         dut.regbank[0] = 16'd50;
-        dut.sram_inst.mem[16'd60] = 16'd100;
-        dut.sram_inst.mem[16'd10] = { 4'b0101, 1'd0, 1'd0, 3'd0, 7'd0 }; // JPR RA, relative, indirect
-        dut.sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd60] = 16'd100;
+        sram_inst.mem[16'd10] = { 4'b0101, 1'd0, 1'd0, 3'd0, 7'd0 }; // JPR RA, relative, indirect
+        sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
         dut.pc = 16'd10;
         expected = 16'd101; // PC ends up at &HLT + 1
 
@@ -288,8 +311,8 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test JPI, absolute addressing, direct
-        dut.sram_inst.mem[16'd0] = { 4'b0110, 1'd1, 1'd1, 10'd123 }; // JPI 123, absolute, direct
-        dut.sram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd0] = { 4'b0110, 1'd1, 1'd1, 10'd123 }; // JPI 123, absolute, direct
+        sram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd124; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -301,8 +324,8 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test JPI, relative addressing, direct
-        dut.sram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd1, -10'd20 }; // JPI -20, relative, direct
-        dut.sram_inst.mem[16'd10] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd1, -10'd20 }; // JPI -20, relative, direct
+        sram_inst.mem[16'd10] = { 4'b1111, 12'd0 }; // HLT
         dut.pc = 16'd30;
         expected = 16'd11; // PC ends up at &HLT + 1
 
@@ -315,9 +338,9 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test JPI, absolute addressing, indirect
-        dut.sram_inst.mem[16'd10] = { 4'b0110, 1'd1, 1'd0, 10'd50 }; // JPI 50, absolute, indirect
-        dut.sram_inst.mem[16'd50] = 16'd123;
-        dut.sram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd10] = { 4'b0110, 1'd1, 1'd0, 10'd50 }; // JPI 50, absolute, indirect
+        sram_inst.mem[16'd50] = 16'd123;
+        sram_inst.mem[16'd123] = { 4'b1111, 12'd0 }; // HLT
         dut.pc = 16'd10;
         expected = 16'd124; // PC ends up at &HLT + 1
 
@@ -330,9 +353,9 @@ module cu_tb();
         rst = 1; #10 rst = 0; #10
 
         // test JPI, relative addressing, indirect
-        dut.sram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd0, -10'd20 }; // JPI -20, relative, indirect
-        dut.sram_inst.mem[16'd10] = 16'd50;
-        dut.sram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd30] = { 4'b0110, 1'd0, 1'd0, -10'd20 }; // JPI -20, relative, indirect
+        sram_inst.mem[16'd10] = 16'd50;
+        sram_inst.mem[16'd50] = { 4'b1111, 12'd0 }; // HLT
         dut.pc = 16'd30;
         expected = 16'd51; // PC ends up at &HLT + 1
 
@@ -347,10 +370,10 @@ module cu_tb();
         // test BRR, absolute addressing, direct, true branch
         dut.regbank[0] = 16'd100;
         dut.regbank[2] = 16'd110;
-        dut.sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.sram_inst.mem[16'd1]   = { 4'b0111, 1'd1, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=ZERO
-        dut.sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
-        dut.sram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        sram_inst.mem[16'd1]   = { 4'b0111, 1'd1, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=ZERO
+        sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd111; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -364,10 +387,10 @@ module cu_tb();
         // test BRR, absolute addressing, direct, false branch
         dut.regbank[0] = 16'd100;
         dut.regbank[2] = 16'd110;
-        dut.sram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.sram_inst.mem[16'd1] = { 4'b0111, 1'd1, 1'd1, 2'd1, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=NEGATIVE
-        dut.sram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT
-        dut.sram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd0] = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        sram_inst.mem[16'd1] = { 4'b0111, 1'd1, 1'd1, 2'd1, 3'd2, 5'd0 }; // BRR RC, absolute, direct, F=NEGATIVE
+        sram_inst.mem[16'd2] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd110] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd3; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -382,10 +405,10 @@ module cu_tb();
         dut.regbank[0] = 16'd100;
         dut.regbank[2] = 16'd109;
         dut.pc = 16'd10;
-        dut.sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.sram_inst.mem[16'd11]  = { 4'b0111, 1'd0, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, direct, F=ZERO
-        dut.sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
-        dut.sram_inst.mem[16'd120] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        sram_inst.mem[16'd11]  = { 4'b0111, 1'd0, 1'd1, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, direct, F=ZERO
+        sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd120] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd121; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -399,11 +422,11 @@ module cu_tb();
         // test BRR, absolute addressing, indirect
         dut.regbank[0] = 16'd100;
         dut.regbank[2] = 16'd110;
-        dut.sram_inst.mem[16'd110] = 16'd200;
-        dut.sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.sram_inst.mem[16'd1]   = { 4'b0111, 1'd1, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, indirect, F=ZERO
-        dut.sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
-        dut.sram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd110] = 16'd200;
+        sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        sram_inst.mem[16'd1]   = { 4'b0111, 1'd1, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, absolute, indirect, F=ZERO
+        sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd201; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -418,11 +441,11 @@ module cu_tb();
         dut.regbank[0] = 16'd100;
         dut.regbank[2] = 16'd109;
         dut.pc = 16'd10;
-        dut.sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.sram_inst.mem[16'd11]  = { 4'b0111, 1'd0, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, indirect, F=ZERO
-        dut.sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
-        dut.sram_inst.mem[16'd120] = 16'd130;
-        dut.sram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        sram_inst.mem[16'd11]  = { 4'b0111, 1'd0, 1'd0, 2'd0, 3'd2, 5'd0 }; // BRR RC, relative, indirect, F=ZERO
+        sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd120] = 16'd130;
+        sram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd131; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -435,10 +458,10 @@ module cu_tb();
 
         // test BRI, absolute addressing, direct, true branch
         dut.regbank[0] = 16'd100;
-        dut.sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.sram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd1, 2'd0, 8'd100 }; // BRI 100, absolute, direct, F=ZERO
-        dut.sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
-        dut.sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        sram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd1, 2'd0, 8'd100 }; // BRI 100, absolute, direct, F=ZERO
+        sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd101; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -451,10 +474,10 @@ module cu_tb();
 
         // test BRI, absolute addressing, direct, false branch
         dut.regbank[0] = 16'd100;
-        dut.sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.sram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd1, 2'd1, 8'd100 }; // BRI 100, absolute, direct, F=NEGATIVE
-        dut.sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
-        dut.sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        sram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd1, 2'd1, 8'd100 }; // BRI 100, absolute, direct, F=NEGATIVE
+        sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd100] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd3; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -468,10 +491,10 @@ module cu_tb();
         // test BRI, relative addressing, direct
         dut.regbank[0] = 16'd100;
         dut.pc = 16'd10;
-        dut.sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.sram_inst.mem[16'd11]  = { 4'b1000, 1'd0, 1'd1, 2'd0, 8'd9 }; // BRI 9, relative, direct, F=ZERO
-        dut.sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
-        dut.sram_inst.mem[16'd20]  = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        sram_inst.mem[16'd11]  = { 4'b1000, 1'd0, 1'd1, 2'd0, 8'd9 }; // BRI 9, relative, direct, F=ZERO
+        sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd20]  = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd21; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -484,11 +507,11 @@ module cu_tb();
 
         // test BRI, absolute addressing, indirect
         dut.regbank[0] = 16'd100;
-        dut.sram_inst.mem[16'd100] = 16'd200;
-        dut.sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.sram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd0, 2'd0, 8'd100 }; // BRI 100, absolute, indirect, F=ZERO
-        dut.sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
-        dut.sram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd100] = 16'd200;
+        sram_inst.mem[16'd0]   = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        sram_inst.mem[16'd1]   = { 4'b1000, 1'd1, 1'd0, 2'd0, 8'd100 }; // BRI 100, absolute, indirect, F=ZERO
+        sram_inst.mem[16'd2]   = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd200] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd201; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
@@ -502,11 +525,11 @@ module cu_tb();
         // test BRI, relative addressing, indirect
         dut.regbank[0] = 16'd100;
         dut.pc = 16'd10;
-        dut.sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
-        dut.sram_inst.mem[16'd11]  = { 4'b1000, 1'd0, 1'd0, 2'd0, 8'd9 }; // BRI 9, relative, indirect, F=ZERO
-        dut.sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
-        dut.sram_inst.mem[16'd20]  = 16'd130;
-        dut.sram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd10]  = { 4'b0000, 3'd1, 3'd0, 3'd0, 3'd1 }; // ALR RB, RA, RA, S=MINUS
+        sram_inst.mem[16'd11]  = { 4'b1000, 1'd0, 1'd0, 2'd0, 8'd9 }; // BRI 9, relative, indirect, F=ZERO
+        sram_inst.mem[16'd12]  = { 4'b1111, 12'd0 }; // HLT
+        sram_inst.mem[16'd20]  = 16'd130;
+        sram_inst.mem[16'd130] = { 4'b1111, 12'd0 }; // HLT
         expected = 16'd131; // PC ends up at &HLT + 1
 
         #200 if (dut.pc == expected) begin
diff --git a/atk16_fpga/top.v b/atk16_fpga/top.v
index 386d6e3..207d41f 100644
--- a/atk16_fpga/top.v
+++ b/atk16_fpga/top.v
@@ -3,12 +3,24 @@
 module top(
     input wire SYSCLK,
     input wire BUT1,
-    output wire LED1
-);
+    output wire LED1,
 
+    output SRAM_CS, // inverted
+    output SRAM_OE, // inverted
+    output SRAM_WE, // inverted
+    output [17:0] SA,
+    inout  [15:0] SD
+);
     cu cu_inst(
         .clk(SYSCLK),
-        .rst(BUT1)
+        .rst(BUT1),
+
+        .sram_cs_n(SRAM_CS),
+        .sram_rd_n(SRAM_OE),
+        .sram_wr_n(SRAM_WE),
+        .sram_addr(SA[15:0]),
+        .sram_in(SD),
+        .sram_out(SD)
     );
 
     assign LED1 = BUT1;